mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
c275218a89
accordance to the newboot document: * reset vector (16 bytes) * vpd (240bytes) * boot block (8k - 256b) * lar archive (256-8 k) The boot block is kind of simple, still. It enables pmode, car, and starts looking for an initram module in the lar archive. Note: This doesnt do much at the moment, as gas seems to produce buggy code in init.S. Take this as a suggestion of how it might work and please provide patches fixing it and bringing it into shape. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@62 f3766cd6-281f-0410-b1cd-43a5c92072e9
91 lines
2.1 KiB
C
91 lines
2.1 KiB
C
/* Should support 8250, 16450, 16550, 16550A type uarts */
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#include <arch/io.h>
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#include <uart8250.h>
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#include "../arch/x86/config.h" // for ttyS0 base FIXME!
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/* Data */
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#define UART_RBR 0x00
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#define UART_TBR 0x00
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/* Control */
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#define UART_IER 0x01
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#define UART_IIR 0x02
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#define UART_FCR 0x02
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#define UART_LCR 0x03
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#define UART_MCR 0x04
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#define UART_DLL 0x00
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#define UART_DLM 0x01
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/* Status */
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#define UART_LSR 0x05
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#define UART_MSR 0x06
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#define UART_SCR 0x07
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static inline int uart8250_can_tx_byte(unsigned base_port)
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{
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return inb(base_port + UART_LSR) & 0x20;
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}
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static inline void uart8250_wait_to_tx_byte(unsigned base_port)
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{
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while(!uart8250_can_tx_byte(base_port))
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;
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}
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static inline void uart8250_wait_until_sent(unsigned base_port)
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{
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while(!(inb(base_port + UART_LSR) & 0x40))
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;
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}
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void uart8250_tx_byte(unsigned base_port, unsigned char data)
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{
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uart8250_wait_to_tx_byte(base_port);
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outb(data, base_port + UART_TBR);
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/* Make certain the data clears the fifos */
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uart8250_wait_until_sent(base_port);
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}
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int uart8250_can_rx_byte(unsigned base_port)
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{
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return inb(base_port + UART_LSR) & 0x01;
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}
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unsigned char uart8250_rx_byte(unsigned base_port)
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{
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while(!uart8250_can_rx_byte(base_port))
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;
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return inb(base_port + UART_RBR);
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}
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void uart8250_init(unsigned base_port, unsigned divisor, unsigned lcs)
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{
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lcs &= 0x7f;
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/* disable interrupts */
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outb(0x0, base_port + UART_IER);
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/* enable fifo's */
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outb(0x01, base_port + UART_FCR);
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/* assert DTR and RTS so the other end is happy */
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outb(0x03, base_port + UART_MCR);
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/* Set Baud Rate Divisor to 12 ==> 115200 Baud */
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outb(0x80 | lcs, base_port + UART_LCR);
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outb(divisor & 0xFF, base_port + UART_DLL);
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outb((divisor >> 8) & 0xFF, base_port + UART_DLM);
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outb(lcs, base_port + UART_LCR);
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}
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/* Initialize a generic uart */
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void init_uart8250(unsigned base_port, struct uart8250 *uart)
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{
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int divisor;
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int lcs;
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divisor = 115200/(uart->baud ? uart->baud: 1);
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lcs = 3;
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if (base_port == TTYS0_BASE) {
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/* Don't reinitialize the console serial port,
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* This is espeically nasty in SMP.
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*/
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return;
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}
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uart8250_init(base_port, divisor, lcs);
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}
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