mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
accordance to the newboot document: * reset vector (16 bytes) * vpd (240bytes) * boot block (8k - 256b) * lar archive (256-8 k) The boot block is kind of simple, still. It enables pmode, car, and starts looking for an initram module in the lar archive. Note: This doesnt do much at the moment, as gas seems to produce buggy code in init.S. Take this as a suggestion of how it might work and please provide patches fixing it and bringing it into shape. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@62 f3766cd6-281f-0410-b1cd-43a5c92072e9
110 lines
2.4 KiB
C
110 lines
2.4 KiB
C
#include <arch/io.h>
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#include <fallback.h>
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/* Base Address */
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#ifndef TTYS0_BASE
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#define TTYS0_BASE 0x3f8
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#endif
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#ifndef TTYS0_BAUD
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#define TTYS0_BAUD 115200
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#endif
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#if ((115200%TTYS0_BAUD) != 0)
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#error Bad ttys0 baud rate
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#endif
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#define TTYS0_DIV (115200/TTYS0_BAUD)
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/* Line Control Settings */
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#ifndef TTYS0_LCS
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/* Set 8bit, 1 stop bit, no parity */
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#define TTYS0_LCS 0x3
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#endif
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#define UART_LCS TTYS0_LCS
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#if CONFIG_USE_INIT == 0
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/* Data */
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#define UART_RBR 0x00
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#define UART_TBR 0x00
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/* Control */
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#define UART_IER 0x01
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#define UART_IIR 0x02
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#define UART_FCR 0x02
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#define UART_LCR 0x03
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#define UART_MCR 0x04
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#define UART_DLL 0x00
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#define UART_DLM 0x01
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/* Status */
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#define UART_LSR 0x05
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#define UART_MSR 0x06
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#define UART_SCR 0x07
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static int uart_can_tx_byte(void)
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{
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return inb(TTYS0_BASE + UART_LSR) & 0x20;
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}
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static void uart_wait_to_tx_byte(void)
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{
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while(!uart_can_tx_byte())
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;
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}
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static void uart_wait_until_sent(void)
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{
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while(!(inb(TTYS0_BASE + UART_LSR) & 0x40))
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;
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}
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static void uart_tx_byte(unsigned char data)
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{
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uart_wait_to_tx_byte();
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outb(data, TTYS0_BASE + UART_TBR);
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/* Make certain the data clears the fifos */
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uart_wait_until_sent();
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}
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void uart_init(void)
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{
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/* disable interrupts */
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outb(0x0, TTYS0_BASE + UART_IER);
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/* enable fifo's */
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outb(0x01, TTYS0_BASE + UART_FCR);
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/* Set Baud Rate Divisor to 12 ==> 115200 Baud */
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outb(0x80 | UART_LCS, TTYS0_BASE + UART_LCR);
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#if USE_OPTION_TABLE == 1
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static const unsigned char divisor[] = { 1,2,3,6,12,24,48,96 };
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unsigned ttys0_div, ttys0_index;
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ttys0_index = read_option(CMOS_VSTART_baud_rate, CMOS_VLEN_baud_rate, 0);
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ttys0_index &= 7;
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ttys0_div = divisor[ttys0_index];
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outb(ttys0_div & 0xff, TTYS0_BASE + UART_DLL);
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outb(0, TTYS0_BASE + UART_DLM);
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#else
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outb(TTYS0_DIV & 0xFF, TTYS0_BASE + UART_DLL);
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outb((TTYS0_DIV >> 8) & 0xFF, TTYS0_BASE + UART_DLM);
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#endif
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outb(UART_LCS, TTYS0_BASE + UART_LCR);
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}
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#else
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extern void uart8250_init(unsigned base_port, unsigned divisor, unsigned lcs);
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void uart_init(void)
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{
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#if USE_OPTION_TABLE == 1
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static const unsigned char divisor[] = { 1,2,3,6,12,24,48,96 };
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unsigned ttys0_div, ttys0_index;
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ttys0_index = read_option(CMOS_VSTART_baud_rate, CMOS_VLEN_baud_rate, 0);
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ttys0_index &= 7;
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ttys0_div = divisor[ttys0_index];
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uart8250_init(TTYS0_BASE, ttys0_div, UART_LCS);
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#else
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uart8250_init(TTYS0_BASE, TTYS0_DIV, UART_LCS);
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#endif
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}
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#endif
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