coreboot for the Switch
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Vadim Bendebury bfa31684a1 rk3399: allow more room for CBMEM console
With recent bootblock code additions the CBMEM console buffer is not
large enough to store the entire log accumulated before DRAM is
initialized, spilling 700 bytes or so on the floor.

This patch adds 1 KB to the CBMEM console buffer, by expense of the
bootblock area in SRAM. The bootblock is taking less then 26K out of
31K allocated for it after this change.

Placing CBMEM console area right after the bootblock makes sure other
memory regions are not going to be affected should memory distribution
between bootblock and CBMEM console need to change again.

BRANCH=none
BUG=none
TEST=examining /sys/firmware/log after device boots up into Chrome OS
     does not report truncated console buffer any more.

Change-Id: I2c3d198803e6f083ddd1d8447aa377ebf85484ce
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/358125
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-06 10:46:18 -07:00
Documentation UPSTREAM: Documentation/Intel/Board: Update the Galileo checklist 2016-06-13 15:55:30 -07:00
payloads UPSTREAM: nvramcui: Update Makefile 2016-06-30 23:10:29 -07:00
src rk3399: allow more room for CBMEM console 2016-07-06 10:46:18 -07:00
util UPSTREAM: rebase.sh: Update to current cros branch 2016-06-30 10:08:27 -07:00
.checkpatch.conf checkpatch: Ignore LINE_SPACING 2016-05-20 18:31:41 +00:00
.clang-format Provide coreboot coding style formalisation file for clang-format 2015-11-10 00:49:03 +01:00
.gitignore gitignore: ignore 3rdparty/blobs 2016-06-23 13:12:07 -07:00
.gitmodules Make upstream tree CrOS SDK friendly 2016-05-12 15:42:17 -06:00
.gitreview add .gitreview 2012-11-01 23:13:39 +01:00
COMMIT-QUEUE.ini Make upstream tree CrOS SDK friendly 2016-05-12 15:42:17 -06:00
COPYING update license template. 2006-08-12 22:03:36 +00:00
MAINTAINERS UPSTREAM: MAINTAINERS: Add myself for Apollolake SoC, FSP2.0, and Amenia mb 2016-05-26 20:37:16 -07:00
Makefile UPSTREAM: Makefile: Make printall target more readable 2016-06-09 02:16:00 -07:00
Makefile.inc UPSTREAM: flashmap: Use CONFIG_ROM_SIZE as flash size in flashmap 2016-06-22 10:41:04 -07:00
PRESUBMIT.cfg Make upstream tree CrOS SDK friendly 2016-05-12 15:42:17 -06:00
README README: improve description of compiler requirements 2015-07-30 05:11:33 +02:00
toolchain.inc toolchain.inc: test IASL by version string instead of number 2016-03-04 16:36:25 +01:00

-------------------------------------------------------------------------------
coreboot README
-------------------------------------------------------------------------------

coreboot is a Free Software project aimed at replacing the proprietary BIOS
(firmware) found in most computers.  coreboot performs a little bit of
hardware initialization and then executes additional boot logic, called a
payload.

With the separation of hardware initialization and later boot logic,
coreboot can scale from specialized applications that run directly
firmware, run operating systems in flash, load custom
bootloaders, or implement firmware standards, like PC BIOS services or
UEFI. This allows for systems to only include the features necessary
in the target application, reducing the amount of code and flash space
required.

coreboot was formerly known as LinuxBIOS.


Payloads
--------

After the basic initialization of the hardware has been performed, any
desired "payload" can be started by coreboot.

See http://www.coreboot.org/Payloads for a list of supported payloads.


Supported Hardware
------------------

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

 * http://www.coreboot.org/Supported_Motherboards
 * http://www.coreboot.org/Supported_Chipsets_and_Devices


Build Requirements
------------------

 * make
 * gcc / g++
   Because Linux distribution compilers tend to use lots of patches. coreboot
   does lots of "unusual" things in its build system, some of which break due
   to those patches, sometimes by gcc aborting, sometimes - and that's worse -
   by generating broken object code.
   Two options: use our toolchain (eg. make crosstools-i386) or enable the
   ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this
   case).
 * iasl (for targets with ACPI support)

Optional:

 * doxygen (for generating/viewing documentation)
 * gdb (for better debugging facilities on some targets)
 * ncurses (for 'make menuconfig' and 'make nconfig')
 * flex and bison (for regenerating parsers)


Building coreboot
-----------------

Please consult http://www.coreboot.org/Build_HOWTO for details.


Testing coreboot Without Modifying Your Hardware
------------------------------------------------

If you want to test coreboot without any risks before you really decide
to use it on your hardware, you can use the QEMU system emulator to run
coreboot virtually in QEMU.

Please see http://www.coreboot.org/QEMU for details.


Website and Mailing List
------------------------

Further details on the project, a FAQ, many HOWTOs, news, development
guidelines and more can be found on the coreboot website:

  http://www.coreboot.org

You can contact us directly on the coreboot mailing list:

  http://www.coreboot.org/Mailinglist


Copyright and License
---------------------

The copyright on coreboot is owned by quite a large number of individual
developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL).
Some files are licensed under the "GPL (version 2, or any later version)",
and some files are licensed under the "GPL, version 2". For some parts, which
were derived from other projects, other (GPL-compatible) licenses may apply.
Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.