mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
bf6d16032e
up correctly on bus 1 --- i.e., the scan of the 8111 bridge works. It even tries to find the vga rom to run it, which we did not get before. the pci bus map built by coreboot matches simnow. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://coreboot.org/repository/coreboot-v3@910 f3766cd6-281f-0410-b1cd-43a5c92072e9
51 lines
1.9 KiB
Makefile
51 lines
1.9 KiB
Makefile
##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2006-2007 coresystems GmbH
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## (Written by Stefan Reinauer <stepan@coresystems.de> for coresystems GmbH)
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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STAGE0_MAINBOARD_SRC := $(src)/lib/clog2.c \
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$(src)/mainboard/$(MAINBOARDDIR)/stage1.c \
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$(src)/arch/x86/stage1_mtrr.c \
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$(src)/arch/x86/amd/model_fxx/dualcore_id.c \
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$(src)/arch/x86/amd/model_fxx/stage1.c \
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$(src)/northbridge/amd/k8/get_nodes.c \
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$(src)/northbridge/amd/k8/libstage1.c \
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INITRAM_SRC= $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
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$(src)/northbridge/amd/k8/raminit.c \
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$(src)/northbridge/amd/k8/dqs.c \
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$(src)/northbridge/amd/k8/reset_test.c \
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$(src)/northbridge/amd/k8/coherent_ht.c \
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$(src)/northbridge/amd/k8/incoherent_ht.c \
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$(src)/northbridge/amd/k8/coherent_ht.c \
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$(src)/arch/x86/pci_ops_conf1.c \
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$(src)/arch/x86/stage1_mtrr.c \
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$(src)/arch/x86/amd/model_fxx/dualcore.c \
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$(src)/arch/x86/amd/model_fxx/fidvid.c \
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$(src)/arch/x86/amd/model_fxx/init_cpus.c \
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$(src)/lib/clog2.c
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STAGE2_MAINBOARD_SRC = mainboard.c
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$(obj)/coreboot.vpd:
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$(Q)printf " BUILD DUMMY VPD\n"
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$(Q)dd if=/dev/zero of=$(obj)/coreboot.vpd bs=256 count=1 $(SILENT)
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