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As documented in DDR3 spec for MR2 the CWL is based on DDR frequency. There's no to little difference for most memory modules operating at DDR3-1333. It might fix problems for memory modules that operate at a higher frequency and memory modules with low CL values should work even better. Tested on Lenovo T420 with DDR3-1333 CL9 and DDR3-1600 CL11. No regressions found. Change-Id: Ib90b5de872a219cf80b4976b6dfae6bc02e298f4 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/17389 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> |
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.. | ||
acpi | ||
arch | ||
commonlib | ||
console | ||
cpu | ||
device | ||
drivers | ||
ec | ||
include | ||
lib | ||
mainboard | ||
northbridge | ||
soc | ||
southbridge | ||
superio | ||
vboot | ||
vendorcode | ||
Kconfig |