mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
b907d321a5
local ints. This is wrong in most coreboot mptables, probably all generated by util/mptable/mptable.c. After fixing this now XP can boot in MPS mode on my M2V. Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5992 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
139 lines
4.2 KiB
C
139 lines
4.2 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007 AMD
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* Written by Yinghai Lu <yinghailu@amd.com> for AMD.
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* Copyright (C) 2009 Harald Gutmann <harald.gutmann@gmx.net>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <console/console.h>
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#include <arch/smp/mpspec.h>
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#include <device/pci.h>
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#include <string.h>
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#include <stdint.h>
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#include <cpu/amd/amdk8_sysconf.h>
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extern unsigned char bus_isa;
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extern unsigned char bus_mcp55[8]; //1
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extern unsigned apicid_mcp55;
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extern unsigned bus_type[256];
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static void *smp_write_config_table(void *v)
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{
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struct mp_config_table *mc;
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unsigned sbdn;
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int i,j,k;
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mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
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mptable_init(mc, "GA-M57SLI-S4", LAPIC_ADDR);
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smp_write_processors(mc);
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get_bus_conf();
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sbdn = sysconf.sbdn;
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/*Bus: Bus ID Type*/
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/* define bus and isa numbers */
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for(j= 0; j < 256 ; j++) {
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if(bus_type[j])
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smp_write_bus(mc, j, "PCI ");
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}
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smp_write_bus(mc, bus_isa, "ISA ");
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/*I/O APICs: APIC ID Version State Address*/
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{
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device_t dev;
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struct resource *res;
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dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0));
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if (dev) {
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res = find_resource(dev, PCI_BASE_ADDRESS_1);
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if (res) {
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smp_write_ioapic(mc, apicid_mcp55, 0x11, res->base);
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}
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/* set up the interrupt registers of mcp55 */
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pci_write_config32(dev, 0x7c, 0xc643c643);
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pci_write_config32(dev, 0x80, 0x8da01009);
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pci_write_config32(dev, 0x84, 0x200018d2);
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}
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}
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mptable_add_isa_interrupts(mc, bus_isa, apicid_mcp55, 0);
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/* PCI interrupts are level triggered, and are
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* associated with a specific bus/device/function tuple.
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*/
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#define PCI_INT(bus, dev, fn, pin) \
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,\
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bus_mcp55[bus], (((dev)<<2)|(fn)), apicid_mcp55, (pin))
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PCI_INT(0,sbdn+1,1, 10); /* SMBus */
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PCI_INT(0,sbdn+2,0, 22); /* USB */
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PCI_INT(0,sbdn+2,1, 23); /* USB */
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PCI_INT(0,sbdn+4,0, 21); /* IDE */
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PCI_INT(0,sbdn+5,0, 20); /* SATA */
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PCI_INT(0,sbdn+5,1, 21); /* SATA */
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PCI_INT(0,sbdn+5,2, 22); /* SATA */
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PCI_INT(0,sbdn+6,1, 23); /* HD Audio */
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PCI_INT(0,sbdn+8,0, 20); /* GBit Ethernet */
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/* The PCIe slots, each on its own bus */
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k = 1;
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for(i=0; i<4; i++){
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for(j=7; j>1; j--){
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if(k>3) k=0;
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PCI_INT(j,0,i, 16+k);
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k++;
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}
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k--;
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}
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/* On bus 1: the PCI bus slots...
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pyhsical PCI slots are j = 7,8
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FireWire is j = 10
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*/
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k=2;
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for(i=0; i<4; i++){
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for(j=6; j<11; j++){
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if(k>3) k=0;
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PCI_INT(1,j,i, 16+k);
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k++;
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}
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}
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/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
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smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
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smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
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/* There is no extension information... */
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/* Compute the checksums */
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mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
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mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
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printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
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mc, smp_next_mpe_entry(mc));
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return smp_next_mpe_entry(mc);
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}
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unsigned long write_smp_table(unsigned long addr)
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{
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void *v;
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v = smp_write_floating_table(addr);
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return (unsigned long)smp_write_config_table(v);
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}
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