switch-coreboot/arch/x86/via
Marc Jones f2872767a2 Add AP detection to stage0 to prevent APs from re-initializing mainboard setup
that has already been done by the BSP. For single processor systems the CPU
flag is always 0, BSP. This code also moves the AP stop for K8 mainboards to
after memory setup so the AP's MTRRs can be setup to match system memory.

Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@1129 f3766cd6-281f-0410-b1cd-43a5c92072e9
2009-02-10 22:41:35 +00:00
..
c7.c This patch fixes a few small problems and gets cn700 to read from an IDE 2008-12-23 23:44:39 +00:00
c7.dts Make C7/CN700 boot to memtest86, and pass that test. Booting is very slow, ~15min to get to a memtest 2008-12-17 21:17:01 +00:00
stage0.S Add AP detection to stage0 to prevent APs from re-initializing mainboard setup 2009-02-10 22:41:35 +00:00
stage1.c Add core2 stage1.c dependency 2008-11-14 05:05:24 +00:00