mirror of
https://github.com/fail0verflow/switch-coreboot.git
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b4fa3fd2ae
Change-Id: I07f4190ab73ec3468e3738be14d64468e2a05720 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8340 Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
131 lines
3.4 KiB
C
131 lines
3.4 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2004 Tyan Computer
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* Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <console/console.h>
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#include <device/device.h>
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#include <device/smbus.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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#include <arch/io.h>
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#include "chip.h"
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static void nic_init(struct device *dev)
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{
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u32 dword, old, mac_h = 0, mac_l = 0;
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int eeprom_valid = 0;
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struct southbridge_nvidia_ck804_config *conf;
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static u32 nic_index = 0;
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u8 *base;
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struct resource *res;
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res = find_resource(dev, 0x10);
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base = res2mmio(res, 0, 0);
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#define NvRegPhyInterface 0xC0
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#define PHY_RGMII 0x10000000
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write32(base + NvRegPhyInterface, PHY_RGMII);
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old = dword = pci_read_config32(dev, 0x30);
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dword &= ~(0xf);
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dword |= 0xf;
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if (old != dword)
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pci_write_config32(dev, 0x30, dword);
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conf = dev->chip_info;
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if (conf->mac_eeprom_smbus != 0) {
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/* Read MAC address from EEPROM at first. */
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struct device *dev_eeprom;
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dev_eeprom = dev_find_slot_on_smbus(conf->mac_eeprom_smbus,
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conf->mac_eeprom_addr);
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if (dev_eeprom) {
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/* If that is valid we will use that. */
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unsigned char dat[6];
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int i, status;
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for (i = 0; i < 6; i++) {
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status = smbus_read_byte(dev_eeprom, i);
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if (status < 0)
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break;
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dat[i] = status & 0xff;
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}
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if (status >= 0) {
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mac_l = 0;
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for (i = 3; i >= 0; i--) {
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mac_l <<= 8;
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mac_l += dat[i];
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}
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if (mac_l != 0xffffffff) {
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mac_l += nic_index;
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mac_h = 0;
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for (i = 5; i >= 4; i--) {
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mac_h <<= 8;
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mac_h += dat[i];
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}
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eeprom_valid = 1;
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}
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}
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}
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}
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/* If that is invalid we will read that from romstrap. */
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if (!eeprom_valid) {
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u32 *mac_pos;
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mac_pos = (u32 *)0xffffffd0; /* See romstrap.inc and romstrap.lds. */
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mac_l = read32(mac_pos) + nic_index;
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mac_h = read32(mac_pos + 1);
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}
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#if 1
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/* Set that into NIC MMIO. */
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#define NvRegMacAddrA 0xA8
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#define NvRegMacAddrB 0xAC
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write32(base + NvRegMacAddrA, mac_l);
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write32(base + NvRegMacAddrB, mac_h);
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#else
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/* Set that into NIC. */
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pci_write_config32(dev, 0xa8, mac_l);
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pci_write_config32(dev, 0xac, mac_h);
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#endif
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nic_index++;
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}
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static struct device_operations nic_ops = {
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.read_resources = pci_dev_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.init = nic_init,
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.scan_bus = 0,
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.ops_pci = &ck804_pci_ops,
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};
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static const struct pci_driver nic_driver __pci_driver = {
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.ops = &nic_ops,
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.vendor = PCI_VENDOR_ID_NVIDIA,
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.device = PCI_DEVICE_ID_NVIDIA_CK804_NIC,
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};
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static const struct pci_driver nic_bridge_driver __pci_driver = {
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.ops = &nic_ops,
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.vendor = PCI_VENDOR_ID_NVIDIA,
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.device = PCI_DEVICE_ID_NVIDIA_CK804_NIC_BRIDGE,
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};
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