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https://github.com/fail0verflow/switch-coreboot.git
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b37fd67e87
This adds important header files that specify calling interface between coreboot and FSP. Change-Id: I393601c91e3c3f630e0fc899f1140ecefed8ecba Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13796 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
11 lines
268 B
Makefile
11 lines
268 B
Makefile
romstage-y += hand_off_block.c
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romstage-y += util.c
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romstage-y += memory_init.c
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ramstage-y += graphics.c
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ramstage-y += hand_off_block.c
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ramstage-y += notify.c
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ramstage-y += silicon_init.c
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ramstage-y += util.c
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CPPFLAGS_common += -I$(src)/drivers/intel/fsp2_0/include
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