mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
af83e1bafb
Sometime we need to pass board specific message to BL31, with that BL31 can do board specific operate base on common code. BRANCH=None BUG=chrome-os-partner:51924 TEST=Build gru Change-Id: Ib7585ce7d3bf01d3ce53b388bf9bd60f3b65f5f1 Signed-off-by: Lin Huang <hl@rock-chips.com> Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/349700 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
85 lines
2.4 KiB
Makefile
85 lines
2.4 KiB
Makefile
##
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## This file is part of the coreboot project.
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##
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## Copyright 2016 Rockchip Inc.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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ifeq ($(CONFIG_SOC_ROCKCHIP_RK3399),y)
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IDBTOOL = util/rockchip/make_idb.py
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bootblock-y += ../common/spi.c
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ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y)
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bootblock-$(CONFIG_DRIVERS_UART) += ../common/uart.c
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endif
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bootblock-y += ../common/gpio.c
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bootblock-y += bootblock.c
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bootblock-y += clock.c
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bootblock-y += gpio.c
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bootblock-y += mmu_operations.c
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bootblock-y += timer.c
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verstage-y += ../common/cbmem.c
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verstage-y += sdram.c
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verstage-y += ../common/spi.c
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verstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c
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verstage-y += clock.c
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verstage-y += timer.c
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################################################################################
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romstage-y += ../common/cbmem.c
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romstage-y += sdram.c
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romstage-y += ../common/spi.c
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romstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c
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romstage-y += clock.c
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romstage-y += mmu_operations.c
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romstage-y += ../common/pwm.c
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romstage-y += timer.c
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romstage-y += romstage.c
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romstage-y += tsadc.c
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romstage-y += usb.c
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romstage-y += gpio.c
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romstage-y += ../common/gpio.c
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################################################################################
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ramstage-y += ../common/cbmem.c
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ramstage-y += sdram.c
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ramstage-y += ../common/spi.c
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ramstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c
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ramstage-y += clock.c
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ramstage-y += display.c
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ramstage-y += ../common/edp.c
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ramstage-y += emmc.c
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ramstage-y += ../common/gpio.c
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ramstage-y += gpio.c
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ramstage-y += ../common/i2c.c
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ramstage-y += saradc.c
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ramstage-y += soc.c
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ramstage-y += timer.c
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ramstage-y += ../common/vop.c
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ramstage-y += usb.c
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ramstage-y += bl31_plat_params.c
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BL31_MAKEARGS += PLAT=rk3399
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################################################################################
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CPPFLAGS_common += -Isrc/soc/rockchip/rk3399/include
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CPPFLAGS_common += -Isrc/soc/rockchip/common/include
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$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin
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@printf "Generating: $(subst $(obj)/,,$(@))\n"
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@mkdir -p $(dir $@)
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@$(IDBTOOL) --from=$< --to=$@ --enable-align --chip=RK33
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endif
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