switch-coreboot/src
Kyösti Mälkki ae7d6ef8b7 Intel model_106cx: change CAR to model_6ex
Diff between model_106cx and model_6ex CAR codes suggests currently
used model_106cx CAR is not optimal - destination RAM and source ROM
of ramstage copy_and_run are only partly set cacheable.

It appears variable MTRR setting for XIP cache is left enabled on
model_106cx code, where it should have extended to cover all of Flash.

Introduces untested functional change on boards:
  intel/d945gclf
  iwave/iWRainbowG6

Deletes file:
  model_106cx/cache_as_ram.inc

Change-Id: I35229f8433927e83821e72e9d9a9fc8fb09c3f1d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/642
Tested-by: build bot (Jenkins)
Reviewed-by: Sven Schnelle <svens@stackframe.org>
2012-07-04 14:45:39 +02:00
..
arch/x86 SMBIOS: move serial number and version out to Kconf 2012-07-03 13:36:27 +02:00
boot Hook up MRC cache update 2012-05-11 00:30:03 +02:00
console Implement %zu / %zd in printk 2012-05-26 07:16:40 +02:00
cpu Intel model_106cx: change CAR to model_6ex 2012-07-04 14:45:39 +02:00
devices Clean up #ifs 2012-05-08 00:34:34 +02:00
drivers Add generic IOAPIC driver 2012-07-04 14:43:23 +02:00
ec Add EC component for SMSC MEC1308/1310 2012-04-02 18:42:40 +02:00
include AGESA F15 wrapper for Trinity 2012-07-03 09:38:55 +02:00
lib Don't loop infinitely long on serial comm failures 2012-05-08 04:34:26 +02:00
mainboard Supermicro X7DB8: add w83793 Hardware monitor 2012-07-04 07:23:03 +02:00
northbridge AGESA F15 wrapper for Trinity 2012-07-03 09:38:55 +02:00
southbridge Fix AMD S3 block generator on Cygwin 2012-07-03 21:02:13 +02:00
superio Unmark source files as executables 2012-05-10 08:44:08 +02:00
vendorcode AGESA F15tn: AMD family15 AGESA code for Trinity 2012-07-03 09:36:35 +02:00
Kconfig Add an option for Waiting for gdb connection if the gdb stub configuration is chosen. 2012-06-23 07:50:07 +02:00
Kconfig.deprecated_options Unify ID_SECTION_OFFSET and mark it deprecated 2012-01-18 11:21:39 +01:00