mirror of
https://github.com/fail0verflow/switch-coreboot.git
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ac490b8a6b
Most things still needs to be filled in, but this will allow us to build boards which use this SOC. BUG=chrome-os-partner:29778 TEST=emerge-veyron coreboot Original-Change-Id: If643d620c5fb8951faaf1ccde400a8e9ed7db3bc Original-Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/205069 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Commit-Queue: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 2f72473a8c2b3fe21d77b351338e6209035878fb) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I53fd0ced42f6ef191d7bf80d8b823bb880344239 Reviewed-on: http://review.coreboot.org/8653 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
49 lines
1.6 KiB
Text
49 lines
1.6 KiB
Text
##
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## This file is part of the coreboot project.
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##
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## Copyright 2014 Rockchip Inc.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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# TODO fill with Versatile Express board data in QEMU.
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chip soc/rockchip/rk3288
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device cpu_cluster 0 on end
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#SCREEN_RGB
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register "screen_type" = "2"
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#LVDS_8BIT_2
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register "lvds_format" = "1"
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#OUT_D888_P666
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register "out_face" = "33"
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register "clock_frequency" = "71000000"
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register "hactive" = "1280"
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register "vactive" = "800"
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register "hback_porch" = "100"
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register "hfront_porch" = "18"
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register "vback_porch" = "8"
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register "vfront_porch" = "6"
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register "hsync_len" = "10"
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register "vsync_len" = "2"
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register "hsync_active" = "0"
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register "vsync_active" = "0"
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register "de_active" = "0"
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register "pixelclk_active" = "0"
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register "swap_rb" = "0"
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register "swap_rg" = "0"
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register "swap_gb" = "0"
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#LCD_EN_GPIO:GPIO7_A3
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register "lcd_en_gpio" = "0xff7e0004"
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#LCD_CS_GPIO:GPIO7_A4
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register "lcd_cs_gpio" = "0xff7e0005"
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end
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