mirror of
https://github.com/fail0verflow/switch-coreboot.git
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abde3b56ce
Secure monitor runs at EL3 and is responsible for jumping to the payload at specified EL and also to manage features like PSCI. Adding basic implementation of secure monitor as a rmodule. Currently, it just jumps to the the payload at current EL. Support for switching el and PSCI will be added as separate patches. CQ-DEPEND=CL:218300 BUG=chrome-os-partner:30785 BRANCH=None TEST=Compiles succesfully and secure monitor loads and runs payload on ryu Change-Id: If0f22299a9bad4e93311154e5546f5bae3f3395c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5e40a21115aeac1cc3c73922bdc3e42d4cdb7d34 Original-Change-Id: I86d5e93583afac141ff61475bd05c8c82d17d926 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/214371 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9080 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
74 lines
1.9 KiB
C
74 lines
1.9 KiB
C
/*
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* This file is part of the coreboot project.
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef _RULES_H
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#define _RULES_H
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/* Useful helpers to tell whether the code is executing in bootblock,
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* romstage, ramstage or SMM.
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*/
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#if defined(__BOOT_BLOCK__)
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#define ENV_BOOTBLOCK 1
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#define ENV_ROMSTAGE 0
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#define ENV_RAMSTAGE 0
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#define ENV_SMM 0
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#define ENV_SECMON 0
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#elif defined(__PRE_RAM__)
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#define ENV_BOOTBLOCK 0
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#define ENV_ROMSTAGE 1
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#define ENV_RAMSTAGE 0
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#define ENV_SMM 0
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#define ENV_SECMON 0
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#elif defined(__SMM__)
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#define ENV_BOOTBLOCK 0
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#define ENV_ROMSTAGE 0
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#define ENV_RAMSTAGE 0
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#define ENV_SMM 1
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#define ENV_SECMON 0
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#elif defined(__SECMON__)
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#define ENV_BOOTBLOCK 0
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#define ENV_ROMSTAGE 0
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#define ENV_RAMSTAGE 0
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#define ENV_SMM 0
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#define ENV_SECMON 1
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#else
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#define ENV_BOOTBLOCK 0
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#define ENV_ROMSTAGE 0
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#define ENV_RAMSTAGE 1
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#define ENV_SMM 0
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#define ENV_SECMON 0
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#endif
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/* For romstage and ramstage always build with simple device model, ie.
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* PCI, PNP and CPU functions operate without use of devicetree.
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*
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* For ramstage individual source file may define __SIMPLE_DEVICE__
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* before including any header files to force that particular source
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* be built with simple device model.
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*/
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#if defined(__PRE_RAM__) || defined(__SMM__)
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#define __SIMPLE_DEVICE__
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#endif
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#endif /* _RULES_H */
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