mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
a73b93157f
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
78 lines
2.8 KiB
Text
78 lines
2.8 KiB
Text
##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2010 Joseph Smith <joe@settoplinux.org>
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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chip northbridge/intel/i82810 # Northbridge
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device cpu_cluster 0 on # APIC cluster
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chip cpu/intel/socket_FC_PGA370 # CPU
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device lapic 0 on end # APIC
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end
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end
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device domain 0 on # PCI domain
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device pci 0.0 on end # Graphics Memory Controller Hub (GMCH)
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device pci 1.0 on end # Chipset Graphics Controller (CGC)
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chip southbridge/intel/i82801bx # Southbridge
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register "pirqa_routing" = "0x05"
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register "pirqb_routing" = "0x06"
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register "pirqc_routing" = "0x07"
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register "pirqd_routing" = "0x09"
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register "pirqe_routing" = "0x0a"
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register "pirqf_routing" = "0x80"
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register "pirqg_routing" = "0x80"
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register "pirqh_routing" = "0x0b"
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register "ide0_enable" = "1"
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register "ide1_enable" = "1"
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device pci 1e.0 on end # PCI bridge
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device pci 1f.0 on # ISA bridge
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chip superio/smsc/smscsuperio # Super I/O (SMSC LPC47M102)
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device pnp 4e.0 on # Floppy
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io 0x60 = 0x3f0
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irq 0x70 = 6
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drq 0x74 = 2
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end
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device pnp 4e.3 on # Parallel port
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io 0x60 = 0x378
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irq 0x70 = 7
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drq 0x74 = 4
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end
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device pnp 4e.4 on # COM1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 4e.5 off end # COM2
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device pnp 4e.7 on # PS/2 keyboard / mouse
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1 # PS/2 keyboard interrupt
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irq 0x72 = 12 # PS/2 mouse interrupt
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end
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device pnp 4e.9 off end # Game port
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device pnp 4e.a on # Runtime registers
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io 0x60 = 0x800
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end
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device pnp 4e.b off end # MPU-401
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end
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end
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device pci 1f.1 on end # IDE
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device pci 1f.2 on end # USB
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device pci 1f.3 on end # SMbus
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device pci 1f.4 on end # USB
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device pci 1f.5 on end # Audio controller
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device pci 1f.6 off end # Modem controller
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end
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end
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end
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