mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
cbe21ed1e1
The coreboot sites support HTTPS, and requests over HTTP with SSL are
also redirected. So use the more secure URLs, which also saves a
request most of the times, as nothing needs to be redirected.
Run the command below to replace all occurences.
```
$ git grep -l -E 'http://(www.|review.|)coreboot.org'
| xargs sed -i 's,http://\(.*\)coreboot.org,https://\1coreboot.org,g'
```
BUG=none
BRANCH=none
TEST=none
Change-Id: I881e55138a6114c67585ce37d4d719fe2626b83a
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: a8843dee58
Original-Change-Id: If53f8b66f1ac72fb1a38fa392b26eade9963c369
Original-Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-on: https://review.coreboot.org/20034
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/528256
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
19 lines
895 B
Text
19 lines
895 B
Text
Summary of Operation
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--------------------
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nvramtool is a utility for reading/writing coreboot parameters and
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displaying information from the coreboot table. It is intended for x86-based
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systems (both 32-bit and 64-bit) that use coreboot.
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The coreboot table resides in low physical memory, and may be accessed
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through the /dev/mem interface. It is created at boot time by coreboot, and
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contains various system information such as the type of mainboard in use. It
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specifies locations in the CMOS (nonvolatile RAM) where the coreboot
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parameters are stored.
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For information about coreboot, see https://www.coreboot.org/.
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Ideas for Future Improvements
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-----------------------------
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1. Move the core functionality of this program into a shared library.
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2. Consider adding options for displaying other BIOS-provided information
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such as the MP table, ACPI table, PCI IRQ routing table, etc.
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