mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
a390d77966
In commit Rudolf Marek discovered, that it is not uniformly written. As
»ASL names are not case-sensitive and will be converted to upper case.« [2]
this change does not have any functional change.
The following command was used to create this patch.
$ git grep -l 'package()' src/mainboard | xargs sed -i 's,package(),Package(),'
[1] http://review.coreboot.org/#/c/3318/
[2] http://www.acpi.info/spec40a.htm
(18.2.1 ASL Names)
Change-Id: I1784dbc50936a1ef9d4376209a3c324ef1fb85cf
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3516
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
340 lines
10 KiB
Text
340 lines
10 KiB
Text
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/*
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DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
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)
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{
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#include "routing.asl"
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}
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*/
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/* Routing is in System Bus scope */
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Scope(\_SB) {
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Name(PR0, Package(){
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/* NB devices */
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/* Bus 0, Dev 0 - RS780 Host Controller */
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/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
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Package(){0x0001FFFF, 0, INTC, 0 },
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Package(){0x0001FFFF, 1, INTD, 0 },
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/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
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Package(){0x0002FFFF, 0, INTC, 0 },
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Package(){0x0002FFFF, 1, INTD, 0 },
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Package(){0x0002FFFF, 2, INTA, 0 },
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Package(){0x0002FFFF, 3, INTB, 0 },
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/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
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Package(){0x0003FFFF, 0, INTD, 0 },
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Package(){0x0003FFFF, 1, INTA, 0 },
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Package(){0x0003FFFF, 2, INTB, 0 },
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Package(){0x0003FFFF, 3, INTC, 0 },
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/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
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Package(){0x0004FFFF, 0, INTA, 0 },
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Package(){0x0004FFFF, 1, INTB, 0 },
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Package(){0x0004FFFF, 2, INTC, 0 },
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Package(){0x0004FFFF, 3, INTD, 0 },
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/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
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Package(){0x0005FFFF, 0, INTB, 0 },
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Package(){0x0005FFFF, 1, INTC, 0 },
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Package(){0x0005FFFF, 2, INTD, 0 },
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Package(){0x0005FFFF, 3, INTA, 0 },
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/* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
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Package(){0x0006FFFF, 0, INTC, 0 },
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Package(){0x0006FFFF, 1, INTD, 0 },
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Package(){0x0006FFFF, 2, INTA, 0 },
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Package(){0x0006FFFF, 3, INTB, 0 },
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/* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
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Package(){0x0007FFFF, 0, INTD, 0 },
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Package(){0x0007FFFF, 1, INTA, 0 },
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Package(){0x0007FFFF, 2, INTB, 0 },
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Package(){0x0007FFFF, 3, INTC, 0 },
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/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
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/* SB devices */
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/* Bus 0, Dev 17 - SATA controller */
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Package(){0x0011FFFF, 0, INTD, 0 },
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/* OHCI, dev 18, 19, 22 func 0
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* EHCI, dev 18, 19, 22 func 2 */
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Package(){0x0012FFFF, 0, INTC, 0 }, /* Dev 12, INTA, handled by INTC device, Global */
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Package(){0x0012FFFF, 1, INTB, 0 }, /* Dev 12, INTB, handled by INTB device, Global */
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Package(){0x0013FFFF, 0, INTC, 0 },
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Package(){0x0013FFFF, 1, INTB, 0 },
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Package(){0x0016FFFF, 0, INTC, 0 },
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Package(){0x0016FFFF, 1, INTB, 0 },
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/* Bus 0, Dev 20 - F0:SMBus/ACPI; F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
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Package(){0x0014FFFF, 0, INTA, 0 },
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Package(){0x0014FFFF, 1, INTB, 0 },
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Package(){0x0014FFFF, 2, INTC, 0 },
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Package(){0x0014FFFF, 3, INTD, 0 },
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Package(){0x0015FFFF, 0, INTA, 0 },
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Package(){0x0015FFFF, 1, INTB, 0 },
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Package(){0x0015FFFF, 2, INTC, 0 },
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Package(){0x0015FFFF, 3, INTD, 0 },
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})
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Name(APR0, Package(){
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/* NB devices in APIC mode */
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/* Bus 0, Dev 0 - RS780 Host Controller */
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/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
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Package(){0x0001FFFF, 0, 0, 18 },
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Package(){0x0001FFFF, 1, 0, 19 },
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/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
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Package(){0x0002FFFF, 0, 0, 18 },
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/* Package(){0x0002FFFF, 1, 0, 19 }, */
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/* Package(){0x0002FFFF, 2, 0, 16 }, */
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/* Package(){0x0002FFFF, 3, 0, 17 }, */
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/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
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Package(){0x0003FFFF, 0, 0, 19 },
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Package(){0x0003FFFF, 1, 0, 16 },
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Package(){0x0003FFFF, 2, 0, 17 },
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Package(){0x0003FFFF, 3, 0, 18 },
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/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
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Package(){0x0004FFFF, 0, 0, 16 },
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Package(){0x0004FFFF, 1, 0, 17 },
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Package(){0x0004FFFF, 2, 0, 18 },
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Package(){0x0004FFFF, 3, 0, 19 },
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/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
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Package(){0x0005FFFF, 0, 0, 17 },
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Package(){0x0005FFFF, 1, 0, 18 },
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Package(){0x0005FFFF, 2, 0, 19 },
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Package(){0x0005FFFF, 3, 0, 16 },
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/* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
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Package(){0x0006FFFF, 0, 0, 18 },
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Package(){0x0006FFFF, 1, 0, 19 },
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Package(){0x0006FFFF, 2, 0, 16 },
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Package(){0x0006FFFF, 3, 0, 17 },
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/* Bus 0, Dev 7 - PCIe Bridge for network card */
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Package(){0x0007FFFF, 0, 0, 19 },
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Package(){0x0007FFFF, 1, 0, 16 },
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Package(){0x0007FFFF, 2, 0, 17 },
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Package(){0x0007FFFF, 3, 0, 18 },
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/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
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/* SB devices in APIC mode */
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/* Bus 0, Dev 17 - SATA controller */
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Package(){0x0011FFFF, 0, 0, 19 },
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/* OHCI, dev 18, 19, 22 func 0
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* EHCI, dev 18, 19, 22 func 2 */
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Package(){0x0012FFFF, 0, 0, 18 },
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Package(){0x0012FFFF, 1, 0, 17 },
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Package(){0x0013FFFF, 0, 0, 18 },
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Package(){0x0013FFFF, 1, 0, 17 },
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Package(){0x0016FFFF, 0, 0, 18 },
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Package(){0x0016FFFF, 1, 0, 17 },
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/* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
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Package(){0x0014FFFF, 0, 0, 16 },
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Package(){0x0014FFFF, 1, 0, 17 },
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Package(){0x0014FFFF, 2, 0, 18 },
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Package(){0x0014FFFF, 3, 0, 19 },
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/* Package(){0x00140004, 2, 0, 18 }, */
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/* Package(){0x00140004, 3, 0, 19 }, */
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/* Package(){0x00140005, 1, 0, 17 }, */
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/* Package(){0x00140006, 1, 0, 17 }, */
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/* TODO: pcie */
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Package(){0x0015FFFF, 0, 0, 16 },
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Package(){0x0015FFFF, 1, 0, 17 },
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Package(){0x0015FFFF, 2, 0, 18 },
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Package(){0x0015FFFF, 3, 0, 19 },
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})
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Name(PR1, Package(){
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/* Internal graphics - RS780 VGA, Bus1, Dev5 */
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Package(){0x0005FFFF, 0, INTA, 0 },
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Package(){0x0005FFFF, 1, INTB, 0 },
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Package(){0x0005FFFF, 2, INTC, 0 },
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Package(){0x0005FFFF, 3, INTD, 0 },
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})
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Name(APR1, Package(){
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/* Internal graphics - RS780 VGA, Bus1, Dev5 */
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Package(){0x0005FFFF, 0, 0, 18 },
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Package(){0x0005FFFF, 1, 0, 19 },
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/* Package(){0x0005FFFF, 2, 0, 20 }, */
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/* Package(){0x0005FFFF, 3, 0, 17 }, */
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})
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Name(PS2, Package(){
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/* The external GFX - Hooked to PCIe slot 2 */
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Package(){0x0000FFFF, 0, INTC, 0 },
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Package(){0x0000FFFF, 1, INTD, 0 },
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Package(){0x0000FFFF, 2, INTA, 0 },
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Package(){0x0000FFFF, 3, INTB, 0 },
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})
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Name(APS2, Package(){
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/* The external GFX - Hooked to PCIe slot 2 */
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Package(){0x0000FFFF, 0, 0, 18 },
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Package(){0x0000FFFF, 1, 0, 19 },
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Package(){0x0000FFFF, 2, 0, 16 },
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Package(){0x0000FFFF, 3, 0, 17 },
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})
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Name(PS4, Package(){
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/* PCIe slot - Hooked to PCIe slot 4 */
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Package(){0x0000FFFF, 0, INTA, 0 },
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Package(){0x0000FFFF, 1, INTB, 0 },
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Package(){0x0000FFFF, 2, INTC, 0 },
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Package(){0x0000FFFF, 3, INTD, 0 },
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})
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Name(APS4, Package(){
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/* PCIe slot - Hooked to PCIe slot 4 */
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Package(){0x0000FFFF, 0, 0, 16 },
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Package(){0x0000FFFF, 1, 0, 17 },
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Package(){0x0000FFFF, 2, 0, 18 },
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Package(){0x0000FFFF, 3, 0, 19 },
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})
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Name(PS5, Package(){
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/* PCIe slot - Hooked to PCIe slot 5 */
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Package(){0x0000FFFF, 0, INTB, 0 },
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Package(){0x0000FFFF, 1, INTC, 0 },
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Package(){0x0000FFFF, 2, INTD, 0 },
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Package(){0x0000FFFF, 3, INTA, 0 },
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})
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Name(APS5, Package(){
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/* PCIe slot - Hooked to PCIe slot 5 */
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Package(){0x0000FFFF, 0, 0, 17 },
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Package(){0x0000FFFF, 1, 0, 18 },
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Package(){0x0000FFFF, 2, 0, 19 },
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Package(){0x0000FFFF, 3, 0, 16 },
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})
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Name(PS6, Package(){
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/* PCIe slot - Hooked to PCIe slot 6 */
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Package(){0x0000FFFF, 0, INTC, 0 },
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Package(){0x0000FFFF, 1, INTD, 0 },
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Package(){0x0000FFFF, 2, INTA, 0 },
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Package(){0x0000FFFF, 3, INTB, 0 },
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})
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Name(APS6, Package(){
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/* PCIe slot - Hooked to PCIe slot 6 */
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Package(){0x0000FFFF, 0, 0, 18 },
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Package(){0x0000FFFF, 1, 0, 19 },
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Package(){0x0000FFFF, 2, 0, 16 },
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Package(){0x0000FFFF, 3, 0, 17 },
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})
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Name(PS7, Package(){
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/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
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Package(){0x0000FFFF, 0, INTD, 0 },
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Package(){0x0000FFFF, 1, INTA, 0 },
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Package(){0x0000FFFF, 2, INTB, 0 },
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Package(){0x0000FFFF, 3, INTC, 0 },
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})
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Name(APS7, Package(){
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/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
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Package(){0x0000FFFF, 0, 0, 19 },
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Package(){0x0000FFFF, 1, 0, 16 },
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Package(){0x0000FFFF, 2, 0, 17 },
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Package(){0x0000FFFF, 3, 0, 18 },
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})
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Name(PE0, Package(){
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/* PCIe slot - Hooked to PCIe slot 10 */
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Package(){0x0000FFFF, 0, INTA, 0 },
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Package(){0x0000FFFF, 1, INTB, 0 },
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Package(){0x0000FFFF, 2, INTC, 0 },
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Package(){0x0000FFFF, 3, INTD, 0 },
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})
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Name(APE0, Package(){
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/* PCIe slot - Hooked to PCIe */
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Package(){0x0000FFFF, 0, 0, 16 },
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Package(){0x0000FFFF, 1, 0, 17 },
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Package(){0x0000FFFF, 2, 0, 18 },
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Package(){0x0000FFFF, 3, 0, 19 },
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})
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Name(PE1, Package(){
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/* PCIe slot - Hooked to PCIe slot 10 */
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Package(){0x0000FFFF, 0, INTB, 0 },
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Package(){0x0000FFFF, 1, INTC, 0 },
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Package(){0x0000FFFF, 2, INTD, 0 },
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Package(){0x0000FFFF, 3, INTA, 0 },
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})
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Name(APE1, Package(){
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/* PCIe slot - Hooked to PCIe */
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Package(){0x0000FFFF, 0, 0, 17 },
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Package(){0x0000FFFF, 1, 0, 18 },
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Package(){0x0000FFFF, 2, 0, 19 },
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Package(){0x0000FFFF, 3, 0, 16 },
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})
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Name(PE2, Package(){
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/* PCIe slot - Hooked to PCIe slot 10 */
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Package(){0x0000FFFF, 0, INTC, 0 },
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Package(){0x0000FFFF, 1, INTD, 0 },
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Package(){0x0000FFFF, 2, INTA, 0 },
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Package(){0x0000FFFF, 3, INTB, 0 },
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})
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Name(APE2, Package(){
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/* PCIe slot - Hooked to PCIe */
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Package(){0x0000FFFF, 0, 0, 18 },
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Package(){0x0000FFFF, 1, 0, 19 },
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Package(){0x0000FFFF, 2, 0, 16 },
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Package(){0x0000FFFF, 3, 0, 17 },
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})
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Name(PE3, Package(){
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/* PCIe slot - Hooked to PCIe slot 10 */
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Package(){0x0000FFFF, 0, INTD, 0 },
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Package(){0x0000FFFF, 1, INTA, 0 },
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Package(){0x0000FFFF, 2, INTB, 0 },
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Package(){0x0000FFFF, 3, INTC, 0 },
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})
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Name(APE3, Package(){
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/* PCIe slot - Hooked to PCIe */
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Package(){0x0000FFFF, 0, 0, 19 },
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Package(){0x0000FFFF, 1, 0, 16 },
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Package(){0x0000FFFF, 2, 0, 17 },
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Package(){0x0000FFFF, 3, 0, 18 },
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})
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Name(PCIB, Package(){
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/* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Func 4. */
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Package(){0x0003FFFF, 0, 0, 0x14 },
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Package(){0x0003FFFF, 1, 0, 0x15 },
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Package(){0x0003FFFF, 2, 0, 0x16 },
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Package(){0x0003FFFF, 3, 0, 0x17 },
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Package(){0x0004FFFF, 0, 0, 0x15 },
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Package(){0x0004FFFF, 1, 0, 0x16 },
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Package(){0x0004FFFF, 2, 0, 0x17 },
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Package(){0x0004FFFF, 3, 0, 0x14 },
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Package(){0x0005FFFF, 0, 0, 0x16 },
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Package(){0x0005FFFF, 1, 0, 0x17 },
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Package(){0x0005FFFF, 2, 0, 0x14 },
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Package(){0x0005FFFF, 3, 0, 0x15 },
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})
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}
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