mirror of
https://github.com/fail0verflow/switch-coreboot.git
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a257efcfcc
Change-Id: I9cb63ff58900a39d7cd8e3da2b9a9a95c2a41a69 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
187 lines
5.9 KiB
C
187 lines
5.9 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include "AGESA.h"
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#include "amdlib.h"
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#include <northbridge/amd/agesa/BiosCallOuts.h>
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#include "Hudson-2.h"
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#include <stdlib.h>
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#include <southbridge/amd/cimx/sb700/gpio_oem.h>
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static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr);
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static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr);
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const BIOS_CALLOUT_STRUCT BiosCallouts[] =
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{
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{AGESA_DO_RESET, agesa_Reset },
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{AGESA_READ_SPD, agesa_ReadSpd },
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{AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported },
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{AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp },
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{AGESA_GNB_PCIE_SLOT_RESET, board_GnbPcieSlotReset },
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{AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData },
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{AGESA_HOOKBEFORE_DRAM_INIT, board_BeforeDramInit },
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{AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, agesa_NoopSuccess },
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{AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess },
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{AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess },
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};
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const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
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/* Call the host environment interface to provide a user hook opportunity. */
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static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr)
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{
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AGESA_STATUS Status;
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UINTN FcnData;
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MEM_DATA_STRUCT *MemData;
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UINT32 AcpiMmioAddr;
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UINT32 GpioMmioAddr;
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UINT8 Data8;
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UINT16 Data16;
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FcnData = Data;
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MemData = ConfigPtr;
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Status = AGESA_SUCCESS;
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/* Get SB MMIO Base (AcpiMmioAddr) */
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WriteIo8 (0xCD6, 0x27);
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Data8 = ReadIo8(0xCD7);
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Data16 = Data8 << 8;
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WriteIo8 (0xCD6, 0x26);
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Data8 = ReadIo8(0xCD7);
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Data16 |= Data8;
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AcpiMmioAddr = (UINT32)Data16 << 16;
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GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
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switch(MemData->ParameterListPtr->DDR3Voltage){
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case VOLT1_35:
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Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
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Data8 &= ~(UINT8)BIT6;
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Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
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Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
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Data8 |= (UINT8)BIT6;
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Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
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break;
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case VOLT1_25:
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Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
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Data8 &= ~(UINT8)BIT6;
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Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
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Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
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Data8 &= ~(UINT8)BIT6;
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Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
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break;
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case VOLT1_5:
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default:
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Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
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Data8 |= (UINT8)BIT6;
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Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
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}
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return Status;
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}
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/* PCIE slot reset control */
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static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr)
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{
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AGESA_STATUS Status;
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UINTN FcnData;
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PCIe_SLOT_RESET_INFO *ResetInfo;
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UINT32 GpioMmioAddr;
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UINT32 AcpiMmioAddr;
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UINT8 Data8;
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UINT16 Data16;
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FcnData = Data;
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ResetInfo = ConfigPtr;
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// Get SB MMIO Base (AcpiMmioAddr)
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WriteIo8(0xCD6, 0x27);
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Data8 = ReadIo8(0xCD7);
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Data16 = Data8 << 8;
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WriteIo8(0xCD6, 0x26);
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Data8 = ReadIo8(0xCD7);
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Data16 |= Data8;
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AcpiMmioAddr = (UINT32)Data16 << 16;
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Status = AGESA_UNSUPPORTED;
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GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
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if (ResetInfo->ResetControl == DeassertSlotReset) {
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if (ResetInfo->ResetId & (BIT2+BIT3)) { //de-assert
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// [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE, SET HIGH
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Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG45);
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if (Data8 & BIT7) {
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Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG28);
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while (!(Data8 & BIT7)) {
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Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG28);
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}
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// GPIO44: PE_GPIO0 MXM Reset
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Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG44);
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Data8 |= BIT6 ;
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Write64Mem8 (GpioMmioAddr+SB_GPIO_REG44, Data8);
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Status = AGESA_SUCCESS;
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}
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} else {
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Status = AGESA_UNSUPPORTED;
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}
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// Travis
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Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG24);
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Data8 |= BIT6;
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Write64Mem8 (GpioMmioAddr+SB_GPIO_REG24, Data8);
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//DE-Assert ALL PCIE RESET
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// APU GPP0 (Dev 4)
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Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
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Data8 |= BIT6;
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Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8);
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// APU GPP1 (Dev 5)
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Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG01);
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Data8 |= BIT6;
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Write64Mem8 (GpioMmioAddr+SB_GPIO_REG01, Data8);
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// APU GPP2 (Dev 6)
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Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG00);
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Data8 |= BIT6;
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Write64Mem8 (GpioMmioAddr+SB_GPIO_REG00, Data8);
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// APU GPP3 (Dev 7)
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Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG27);
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Data8 |= BIT6;
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Write64Mem8 (GpioMmioAddr+SB_GPIO_REG27, Data8);
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} else {
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if (ResetInfo->ResetId & (BIT2+BIT3)) { //Pcie Slot Reset is supported
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// GPIO44: PE_GPIO0 MXM Reset
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Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG44);
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Data8 &= ~(UINT8)BIT6;
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Write64Mem8 (GpioMmioAddr+SB_GPIO_REG44, Data8);
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Status = AGESA_SUCCESS;
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}
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// Travis
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Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG24);
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Data8 &= ~(UINT8)BIT6;
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Write64Mem8 (GpioMmioAddr+SB_GPIO_REG24, Data8);
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//Assert ALL PCIE RESET
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// APU GPP0 (Dev 4)
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Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
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Data8 &= ~(UINT8)BIT6;
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Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8);
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// APU GPP1 (Dev 5)
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Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG01);
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Data8 &= ~(UINT8)BIT6;
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Write64Mem8 (GpioMmioAddr+SB_GPIO_REG01, Data8);
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// APU GPP2 (Dev 6)
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Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG00);
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Data8 &= ~(UINT8)BIT6;
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Write64Mem8 (GpioMmioAddr+SB_GPIO_REG00, Data8);
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// APU GPP3 (Dev 7)
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Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG27);
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Data8 &= ~(UINT8)BIT6;
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Write64Mem8 (GpioMmioAddr+SB_GPIO_REG27, Data8);
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}
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return Status;
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}
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