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https://github.com/fail0verflow/switch-coreboot.git
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ff7df4f7ad
code (This goes hand in hand, as some parts of serial were hardcoded to one architecture until now) * include/uart8250.h: add TTYSx defines that are used in multiple places. formerly part of arch/x86/serial.c. Drop init_uart8250 (unused) * lib/uart8250.c: drop arch/x86/config.h usage Drop init_uart8250 (unused) * arch/powerpc/Kconfig, arch/x86/Kconfig: add CONFIG_ARCH to contain the directory name under LinuxBIOSv3/arch/ * arch/x86/console.c: drop some dead code. Drop hardcoded config.h values. use generic uart8250.h header * arch/x86/cachemain.c: Drop hardcoded config.h values. Still use hardcoded ROM size for now. (To be changed later) * arch/x86/config.h: dropped, no longer needed * arch/x86/serial.c: factor out generically used defines to uart8250.h * Makefile: use mainboard architecture instead of target architecture to choose include path. Read .xcompile if available (configure replacement). Create build.h with compile time and version. * util/xcompile/xcompile: new file. Search for supported cross compilers linkers, assemblers (and potentially supported compiler flags etc) This is a very slick configure replacement. * util/dtc/Makefile: fix Makefile for cross compilation Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@190 f3766cd6-281f-0410-b1cd-43a5c92072e9
76 lines
1.7 KiB
C
76 lines
1.7 KiB
C
/* Should support 8250, 16450, 16550, 16550A type uarts */
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#include <arch/io.h>
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#include <uart8250.h>
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/* Data */
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#define UART_RBR 0x00
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#define UART_TBR 0x00
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/* Control */
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#define UART_IER 0x01
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#define UART_IIR 0x02
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#define UART_FCR 0x02
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#define UART_LCR 0x03
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#define UART_MCR 0x04
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#define UART_DLL 0x00
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#define UART_DLM 0x01
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/* Status */
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#define UART_LSR 0x05
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#define UART_MSR 0x06
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#define UART_SCR 0x07
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static inline int uart8250_can_tx_byte(unsigned base_port)
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{
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return inb(base_port + UART_LSR) & 0x20;
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}
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static inline void uart8250_wait_to_tx_byte(unsigned base_port)
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{
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while(!uart8250_can_tx_byte(base_port))
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;
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}
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static inline void uart8250_wait_until_sent(unsigned base_port)
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{
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while(!(inb(base_port + UART_LSR) & 0x40))
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;
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}
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void uart8250_tx_byte(unsigned base_port, unsigned char data)
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{
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uart8250_wait_to_tx_byte(base_port);
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outb(data, base_port + UART_TBR);
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/* Make certain the data clears the fifos */
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uart8250_wait_until_sent(base_port);
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}
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int uart8250_can_rx_byte(unsigned base_port)
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{
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return inb(base_port + UART_LSR) & 0x01;
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}
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unsigned char uart8250_rx_byte(unsigned base_port)
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{
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while(!uart8250_can_rx_byte(base_port))
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;
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return inb(base_port + UART_RBR);
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}
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/* Initialize a generic uart */
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void uart8250_init(unsigned base_port, unsigned divisor, unsigned lcs)
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{
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lcs &= 0x7f;
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/* disable interrupts */
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outb(0x0, base_port + UART_IER);
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/* enable fifo's */
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outb(0x01, base_port + UART_FCR);
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/* assert DTR and RTS so the other end is happy */
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outb(0x03, base_port + UART_MCR);
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/* Set Baud Rate Divisor to 12 ==> 115200 Baud */
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outb(0x80 | lcs, base_port + UART_LCR);
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outb(divisor & 0xFF, base_port + UART_DLL);
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outb((divisor >> 8) & 0xFF, base_port + UART_DLM);
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outb(lcs, base_port + UART_LCR);
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}
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