switch-coreboot/src
William wu 9f470b1930 google/gru: Tune USB 2.0 PHY to increase compatibility
When testing USB 2.0 compatibility with different kinds
of USB 2.0 devices on Kevin board, we find that some
USB HDDs (e.g. seagate SRD00F1 1TB HDD) and some smart
phones (e.g. galaxy A5 smart phone) can't be detected.
And according to the error log, this issue is related
to USB 2.0 PHY signal problem.

For the USB HDD, error log is:
[  592.557724] usb 5-1: new high-speed USB device number 2 using xhci-hcd
[  592.847735] usb 5-1: new high-speed USB device number 3 using xhci-hcd
[  593.473720] usb 5-1: new high-speed USB device number 6 using xhci-hcd
[  594.187717] usb 5-1: new high-speed USB device number 9 using xhci-hcd
[  595.020717] usb 5-1: new high-speed USB device number 13 using xhci-hcd
[  595.284730] usb 5-1: new high-speed USB device number 14 using xhci-hcd
[  595.574816] usb 5-1: new high-speed USB device number 15 using xhci-hcd

The log shows that HDD failed to high-speed handshake.

For the smart phone, error log is:
[ 1145.661625] usb 5-1: new high-speed USB device number 2 using xhci-hcd
[ 1145.771674] usb 5-1: device descriptor read/64, error -71
[ 1145.979752] usb 5-1: device descriptor read/64, error -71
[ 1146.187721] usb 5-1: new high-speed USB device number 3 using xhci-hcd
[ 1146.301754] usb 5-1: device descriptor read/64, error -71
[ 1146.509750] usb 5-1: device descriptor read/64, error -71
[ 1146.717722] usb 5-1: new high-speed USB device number 4 using xhci-hcd
[ 1146.724393] usb 5-1: Device not responding to setup address.
[ 1146.930795] usb 5-1: Device not responding to setup address.
[ 1147.137720] usb 5-1: device not accepting address 4, error -71
[ 1147.246644] usb 5-1: new high-speed USB device number 5 using xhci-hcd
[ 1147.253336] usb 5-1: Device not responding to setup address.
[ 1147.459786] usb 5-1: Device not responding to setup address.
[ 1147.665712] usb 5-1: device not accepting address 5, error -71
[ 1147.671789] usb usb5-port1: unable to enumerate USB device

The log shows that smart phone failed to read device
descriptor, error -71 may be caused by PHY signal problem.

This patch aims to tune USB 2.0 PHY with the following
parameters to support USB HDD, smart phone and some other
potential USB 2.0 devices.

1. Disable the pre-emphasize in chirp state to avoid
   high-speed handshake failure.

2. Bypass ODT auto compensation to enable set max driver
   strength manually. (Bit[42] of usbphy_ctrl register is
   1'b1 for bypass, and Bit[41:37] of usbphy_ctrl register
   is 5'b10000 for max driver strength).

3. Bypass ODT auto refresh, and set the max bias current
   tuning reference. (Bit[57] of usbphy_ctrl register is
   1'b1 for bypass, and Bit[52:50] of usbphy_ctrl register
   is 3b'100  for max bias current tuning reference).

We have done the USB 2.0 compliance test and compatibility test
with this patch, it works well.

BRANCH=gru
BUG=chrome-os-partner:59623
TEST=plug/unplug USB HDD or smart phone in Type-C port,
check if they can be detected successfully.

Change-Id: I275c2236b8e469bfd04e9184d007eb095657225e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7735c514d4
Original-Change-Id: I4e6c10faa1c03af9880a89afe4731a7065eb1e4e
Original-Signed-off-by: William wu <wulf@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/409856
Original-Commit-Ready: Eddie Cai <eddie.cai.rk@gmail.com>
Original-Tested-by: Cindy Han <cindy.han@samsung.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/17566
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-29 17:44:10 +01:00
..
acpi src/acpi: Capitalize ACPI and SATA 2016-07-31 19:25:40 +02:00
arch Build system: Update HAVE_CMOS_DEFAULT 2016-11-28 18:58:15 +01:00
commonlib commonlib/include: remove NEED_VB20_INTERNALS 2016-11-19 16:57:27 +01:00
console console/vtxprintf.c: cast precision to size_t for string length 2016-11-21 23:44:18 +01:00
cpu AGESA binaryPI: Fix cache-as-ram for x86_64 2016-11-25 10:32:07 +01:00
device device/dram/ddr3: Fix calculation CRC16 of SPD 2016-11-21 02:21:17 +01:00
drivers Build system: Update HAVE_CMOS_DEFAULT 2016-11-28 18:58:15 +01:00
ec google/parrot: Fix keyboard interrupts, DSDT 2016-11-25 20:50:00 +01:00
include x86 BIST: Fix missing include 2016-11-24 21:39:41 +01:00
lib intel post-car: Increase stacktop alignment 2016-11-18 20:59:12 +01:00
mainboard google/gru: Tune USB 2.0 PHY to increase compatibility 2016-11-29 17:44:10 +01:00
northbridge nb/intel/i945/gma: Declare count variable outside 'for' loop 2016-11-29 17:21:30 +01:00
soc intel/sch: Switch to MMCONF_SUPPORT_DEFAULT 2016-11-29 17:07:24 +01:00
southbridge sb/intel/i3100/lpc.c: Use tab for indents 2016-11-28 01:06:33 +01:00
superio sio/nuvoton: Include generic nuvoton driver in bootblock stage 2016-11-28 20:33:21 +01:00
vboot commonlib/include: remove NEED_VB20_INTERNALS 2016-11-19 16:57:27 +01:00
vendorcode vendorcode/siemens: Add HWID to hwilib 2016-11-24 19:23:50 +01:00
Kconfig Remove explicit select MMCONF_SUPPORT 2016-11-22 04:15:11 +01:00