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https://github.com/fail0verflow/switch-coreboot.git
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62f8ea8e9b
This means that basic resource maps are working, initial hypertransport setup is working, the amd8111 ISA device is working, config space is working for all the parts, we can grow the FLASH part address space to more than 64k, and in general we're having a good time. Here is the output: coreboot-3.0.824 Tue Aug 26 22:18:21 PDT 2008 starting... (console_loglevel=8) Choosing fallback boot. LAR: Attempting to open 'fallback/initram/segment0'. LAR: Start 0xfff80000 len 0x80000 LAR: normal/option_table@0xfff80000, size 1776 LAR: normal/initram/segment0@0xfff80740, size 24404 LAR: normal/stage2/segment0@0xfff866f0, size 1 LAR: normal/stage2/segment1@0xfff86750, size 18542 LAR: normal/stage2/segment2@0xfff8b010, size 559 LAR: normal/payload/segment0@0xfff8b290, size 18142 LAR: bootblock@0xffff7fc0, size 32768 LAR: File not found! LAR: Run file fallback/initram/segment0 failed: No such file. Fallback failed. Try normal boot LAR: Attempting to open 'normal/initram/segment0'. LAR: Start 0xfff80000 len 0x80000 LAR: normal/option_table@0xfff80000, size 1776 LAR: normal/initram/segment0@0xfff80740, size 24404 LAR: CHECK normal/initram/segment0 @ 0xfff80740 start 0xfff80790 len 24404 reallen 24404 compression 0 entry 0x00000004 loadaddress 0x00000000 Entry point is 0xfff80794 Hi there from stage1 stage1 returns run_file returns with 0 Goal for tomorrow is to get initram done. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://coreboot.org/repository/coreboot-v3@826 f3766cd6-281f-0410-b1cd-43a5c92072e9 |
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| .. | ||
| agp_device.c | ||
| cardbus_device.c | ||
| device.c | ||
| device_util.c | ||
| hypertransport.c | ||
| Kconfig | ||
| Makefile | ||
| pci_device.c | ||
| pci_ops.c | ||
| pci_rom.c | ||
| pcie_device.c | ||
| pcix_device.c | ||
| pnp_device.c | ||
| pnp_raw.c | ||
| root_device.c | ||
| smbus_ops.c | ||