switch-coreboot/src
Rizwan Qureshi 952cb03b9e intel/skylake: FSP 1.7.0 MemoryInit/SiliconInit params update
In FSP 1.7.0 SataMode and SataEnable have been moved from
MemoryInit to SiliconInit. Also, GpioTablePtr has been removed.

USB phy settings added to SiliconInit, Enable the configs for USB
equalization settings in coreboot.

Addition of serialIO UPD to indicate FSP not to reinitialise
UART2 controller during MemoryInit.

BRANCH=none BUG=chrome-os-partner:45684, chrome-os-partner:42284, chrome-os-partner:41374
TEST=build for Kunimitsu, boot on FAB3, Also checked for Boot from USB, Boot from eMMC,
	USB Audio, Onboard Audio, Touch, Wifi, S3 entry/resume

CQ-DEPEND=CL:*232947, CL:*232946, CL:*232948, CL:*232949

Change-Id: I2e8e6e32fc7074774ddcf1fb4c270bb56372b7df
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 623c5a52f3afedaf2c0bfe7361cfd627d093cb73
Original-Change-Id: I8b3be2c49893c564fe2197aa32bde6323bf425e9
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Signed-off-by: Rishavnath Satapathy <rishavnath.satapathy@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/303661
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12144
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-27 15:15:39 +01:00
..
acpi
arch armv7: Word-sized/half-word-sized memory operations for 32/16 bit read/write 2015-10-17 18:10:29 +00:00
commonlib vboot: prepare for x86 verstage 2015-10-11 23:57:29 +00:00
console x86: add standalone verstage support 2015-10-14 17:07:52 +00:00
cpu cpu/amd/car: Add initial Suspend to RAM (S3) support 2015-10-27 15:12:08 +01:00
device yabel: explicitly cast values to match printk expectations 2015-10-25 07:29:55 +01:00
drivers fsp/intel common: Add support for Gfx PEIM (AKA GOP) 2015-10-27 15:15:15 +01:00
ec ec/google: Move label to BOL to satisfy lint-tests 2015-10-15 07:36:26 +00:00
include coreboot: make lb_framebuffer a weak function 2015-10-27 15:15:09 +01:00
lib coreboot: make lb_framebuffer a weak function 2015-10-27 15:15:09 +01:00
mainboard intel/kunimitsu Fab3: Strengthening Rcomp target CTRL value 2015-10-27 15:15:30 +01:00
northbridge northbridge/amd/amdfam10: Limit maximum RAM clock to BKDG recommendations 2015-10-27 05:31:57 +01:00
soc intel/skylake: FSP 1.7.0 MemoryInit/SiliconInit params update 2015-10-27 15:15:39 +01:00
southbridge southbridge/amd/sr5650: Add AMD Family 15h CPU support 2015-10-26 07:32:58 +01:00
superio superio/nuvoton/nct5572d: Enable power state after power failure support 2015-10-23 20:04:07 +02:00
vendorcode amd/sb800: Make UsbRxMode per-board customizable 2015-10-24 00:21:01 +02:00
Kconfig Separate bootsplash image menuconfig option from others 2015-10-25 07:28:38 +01:00