mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
c275218a89
accordance to the newboot document: * reset vector (16 bytes) * vpd (240bytes) * boot block (8k - 256b) * lar archive (256-8 k) The boot block is kind of simple, still. It enables pmode, car, and starts looking for an initram module in the lar archive. Note: This doesnt do much at the moment, as gas seems to produce buggy code in init.S. Take this as a suggestion of how it might work and please provide patches fixing it and bringing it into shape. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@62 f3766cd6-281f-0410-b1cd-43a5c92072e9
148 lines
3.5 KiB
ArmAsm
148 lines
3.5 KiB
ArmAsm
# init code - switch cpu to pmode and enable cache as ram.
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#
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# Copyright (C) 2000 Ron Minnich, Advanced Computing Lab, LANL
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# Copyright (C) 2007 Stefan Reinauer, coresystems GmbH
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; version 2 of the License.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
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#
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#include "macros.h"
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#define ROM_CODE_SEG 0x08
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#define ROM_DATA_SEG 0x10
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#define CACHE_RAM_CODE_SEG 0x18
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#define CACHE_RAM_DATA_SEG 0x20
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.code16
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.globl _start
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_start:
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cli
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/* save the BIST result */
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movl %eax, %ebp;
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/* thanks to kmliu@sis.tw.com for this TBL fix */
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/* IMMEDIATELY invalidate the translation lookaside buffer before
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* executing any further code. Even though paging is disabled we
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* could still get false address translations due to the TLB if we
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* didn't invalidate it.
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*/
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xorl %eax, %eax
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movl %eax, %cr3 /* Invalidate TLB */
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/* switch to protected mode */
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movw %cs, %ax
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shlw $4, %ax
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movw $gdt16 + 0xe000, %bx
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subw %ax, %bx
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data32 lgdt %cs:(%bx)
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movl %cr0, %eax
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andl $0x7FFAFFD1, %eax /* PG,AM,WP,NE,TS,EM,MP = 0 */
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orl $0x60000001, %eax /* CD, NW, PE = 1 */
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movl %eax, %cr0
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/* Restore BIST result */
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movl %ebp, %eax
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// port80_post (0x23) /* post 0x01 */
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/* Now we are in protected mode. Jump to a 32 bit code segment. */
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//data32 ljmp $ROM_CODE_SEG, $__protected_start
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data32 ljmp $ROM_CODE_SEG, $0xe058
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.align 4
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.globl gdt16
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gdt16 = . - _start
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.word gdt_end - gdt -1 /* compute the table limit */
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.long gdt /* we know the offset */
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/* From now on we are 32bit */
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.code32
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/* This is the gdt for ROMCC/ASM part of LinuxBIOS. It
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* is different from the gdt in GCC part of LinuxBIOS.
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*
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* That on was defined in c_start.S in LinuxBIOS v2. TODO
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*/
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.align 4
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.globl gdtptr
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gdt:
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gdtptr:
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.word gdt_end - gdt -1 /* compute the table limit */
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.long gdt /* we know the offset */
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.word 0
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/* selgdt 0x08, flat code segment */
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.word 0xffff, 0x0000
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.byte 0x00, 0x9b, 0xcf, 0x00
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/* selgdt 0x10,flat data segment */
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.word 0xffff, 0x0000
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.byte 0x00, 0x93, 0xcf, 0x00
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gdt_end:
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/*
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* When we come here we are in protected mode. We expand
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* the stack and copies the data segment from ROM to the
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* memory.
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*
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* After that, we call the chipset bootstrap routine that
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* does what is left of the chipset initialization.
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*
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* NOTE aligned to 4 so that we are sure that the prefetch
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* cache will be reloaded.
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*/
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.align 4
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#if 0
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//This code was used by v2. TODO
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.globl protected_start
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protected_start:
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lgdt %cs:gdtptr
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ljmp $ROM_CODE_SEG, $__protected_start
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#endif
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.globl __protected_start
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__protected_start:
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/* Save the BIST value */
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movl %eax, %ebp
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port80_post (0x01) /* post 0x01 */
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movw $ROM_DATA_SEG, %ax
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movw %ax, %ds
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movw %ax, %es
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movw %ax, %ss
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movw %ax, %fs
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movw %ax, %gs
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/* Restore the BIST value to %eax */
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movl %ebp, %eax
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#define CONFIG_CPUTYPE_INTEL 1
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#ifdef CONFIG_CPUTYPE_INTEL
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#include "cache_as_ram.S"
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#endif
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.align 4
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