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https://github.com/fail0verflow/switch-coreboot.git
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01464a69b8
Initial files to support the Intel Skylake RVP3 Matches chromium tree at 927026db This board uses the Skylake FSP 1.1 image and does not build without the FspUpdVpd.h file. BRANCH=none BUG=None TEST=Build and run on sklrvp Change-Id: I5e7fff8f62a737e627e25c1e03e343d6167041ea Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10343 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
35 lines
1.1 KiB
C
35 lines
1.1 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Google Inc.
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* Copyright (C) 2015 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc.
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*/
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#ifndef _MAINBOARD_THERMAL_H_
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#define _MAINBOARD_THERMAL_H_
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#define TEMPERATURE_SENSOR_ID 0 /* PECI */
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/* Temperature which OS will shutdown at */
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#define CRITICAL_TEMPERATURE 104
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/* Temperature which OS will throttle CPU */
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#define PASSIVE_TEMPERATURE 95
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/* Tj_max value for calculating PECI CPU temperature */
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#define MAX_TEMPERATURE 105
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#endif /* _MAINBOARD_THERMAL_H_ */
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