mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
8e3464109e
* src/cpu/amd/model_lx/model_lx_init.c L2 cache initialization removed (moved to northbridge.c) * src/include/cpu/amd/lxdef.h more checked values * src/northbridge/amd/lx/northbridge.c L2 cache initialization added cpubug() commented out * src/northbridge/amd/lx/raminit.c empty function sdram_set_registers() is in use, don't remove * src/mainboard/artecgroup/dbe61/Config.lb irqmap changes * src/mainboard/artecgroup/dbe61/irq_tables.c tentative changes to irq table (currently not in use) * src/mainboard/artecgroup/dbe61/mainboard.c irq assigned manually to NIC * src/mainboard/artecgroup/dbe61/Options.lb gcc 4.0 is OK * targets/artecgroup/dbe61/Config.lb 64K for VSA is OK at moment Signed-off-by: Indrek Kruusa <indrek.kruusa@artecdesign.ee> Signed-off-by: Andrei Birjukov <andrei.birjukov@artecdesign.ee> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2360 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 |
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| .. | ||
| arch | ||
| boot | ||
| config | ||
| console | ||
| cpu | ||
| devices | ||
| drivers | ||
| include | ||
| lib | ||
| mainboard | ||
| northbridge | ||
| pc80 | ||
| pmc/altimus/mpc7410 | ||
| ram | ||
| sdram | ||
| southbridge | ||
| stream | ||
| superio | ||