switch-coreboot/src
Edward O'Callaghan 8cc5dc1dd2 soc/intel/broadwell/me.c: Prevent unused function warning
Put function under same guard as its call site so that the
compiler does not emit a warn about unused functions upon
a false branch of the guard.

Change-Id: I899d539ec5fbb87e7469415cc8d15837ba8e63f3
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8156
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Tested-by: build bot (Jenkins)
2015-01-12 19:05:46 +01:00
..
arch ACPI: Add acpi_is_wakeup_s3() for romstage 2015-01-10 13:53:51 +01:00
console misc: Drop print_ implementation from non-romcc boards 2015-01-09 06:12:22 +01:00
cpu ACPI: Add acpi_is_wakeup_s3() for romstage 2015-01-10 13:53:51 +01:00
device doxygen fixes: fix parameter names to match the functions 2015-01-06 06:32:37 +01:00
drivers elog: Add ELOG_TYPE_BOOT event using fake boot count if necessary 2015-01-09 07:46:56 +01:00
ec chrome ec: Add ACPI Device for ALS if enabled 2015-01-09 07:43:34 +01:00
include Primitive memory test 2015-01-09 16:50:55 +01:00
lib Primitive memory test 2015-01-09 16:50:55 +01:00
mainboard mainboard/lenovo/?/Kconfig: select NO_UART_ON_SUPERIO 2015-01-12 15:50:08 +01:00
northbridge ACPI: Add acpi_is_wakeup_s3() for romstage 2015-01-10 13:53:51 +01:00
soc soc/intel/broadwell/me.c: Prevent unused function warning 2015-01-12 19:05:46 +01:00
southbridge ACPI: Add acpi_is_wakeup_s3() for romstage 2015-01-10 13:53:51 +01:00
superio superio: Drop print_ implementation from non-romcc boards 2015-01-06 20:14:19 +01:00
vendorcode elog: Add function to log boot reason in ChromeOS case 2015-01-03 00:25:27 +01:00
Kconfig Allow RISCV to be compiled with ANY_TOOLCHAIN 2015-01-02 18:44:57 +01:00