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switch-coreboot/src
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jinkun.hong 8cc3a2a467 rk3288: support single channel ddr 
When using single-channel ddr, DMC channel 1 need to reset dll,
otherwise it will lead to pmdomain idle request fails.

BUG=chrome-os-partner:35654
BRANCH=veyron
TEST=boot rialto

Change-Id: Id6b673187c688d238e9a391b3d98720c783e3af4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 927e8426104f8869e139c3f60a04cd49bf726e61
Original-Change-Id: I8be1567040ddb5f2a2b0d06568e517d794ead87a
Original-Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/250060
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/9819
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21 08:12:43 +02:00
..
arch urara: Identity map DRAM/SRAM 2015-04-21 08:12:13 +02:00
console Add console wrapper for UART driver 2015-04-14 21:25:34 +02:00
cpu uart: pass register width in the coreboot table 2015-04-17 09:53:39 +02:00
device rk3288: Add software I2C support 2015-04-17 09:59:19 +02:00
drivers flash: use two bytes of device ID to identify stmicro chips 2015-04-17 10:10:52 +02:00
ec chromeec: Fix printf formatting warning 2015-04-14 09:01:03 +02:00
include Arrange CBMEM table entries' IDs alphanumerically 2015-04-21 08:08:19 +02:00
lib chromeos: vboot2: Add TPM PCR extension support 2015-04-20 17:06:28 +02:00
mainboard urara: add config of SPI bus and correct selection of winbond flash 2015-04-21 08:08:12 +02:00
northbridge northbridge/amd/agesa/familyXY: Make NULL device op explicit 2015-04-09 19:34:22 +02:00
soc rk3288: support single channel ddr 2015-04-21 08:12:43 +02:00
southbridge southbridge/intel/bd82x6x: Add LPC id 0x1e49 for B75 chipset 2015-04-20 23:51:34 +02:00
superio kconfig: drop intermittend forwarder files 2015-04-07 17:40:28 +02:00
vendorcode chromeos: vboot2: Add TPM PCR extension support 2015-04-20 17:06:28 +02:00
Kconfig rk3288: Disable ramstage compression by default 2015-04-20 10:19:56 +02:00