mirror of
https://github.com/fail0verflow/switch-coreboot.git
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8accd6f043
Three things are required to enable wake-on-usb: 1. 5V to USB ports should be enabled in S3. 2. ASL file needs to have appropriate wake bit set. 3. XHCI controller should have the wake on attach/detach bit set for the corresponding port in PORTSCN register. Only part missing was #3. This CL adds support to allow mainboard to define a bitmap in devicetree corresponding to the ports that it wants to enable wake-on-usb feature. Based on the bitmap, wake on attach/detach bits in PORTSCN would be set by xhci.asl for the appropriate ports. BUG=chrome-os-partner:58734 BRANCH=None TEST=Verified that with port 5 enabled, chell wakes up from S3 on usb attach/detach. Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17056 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I40a22a450e52f74a0ab93ebb8170555d834ebdaf Reviewed-on: https://chromium-review.googlesource.com/403845 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
97 lines
2.8 KiB
Text
97 lines
2.8 KiB
Text
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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* Copyright (C) 2014 Google Inc.
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* Copyright (C) 2015 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/* Global Variables */
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Name (\PICM, 0) // IOAPIC/8259
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/*
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* Global ACPI memory region. This region is used for passing information
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* between coreboot (aka "the system bios"), ACPI, and the SMI handler.
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* Since we don't know where this will end up in memory at ACPI compile time,
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* we have to fix it up in coreboot's ACPI creation phase.
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*/
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External (NVSA)
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OperationRegion (GNVS, SystemMemory, NVSA, 0x2000)
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Field (GNVS, ByteAcc, NoLock, Preserve)
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{
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/* Miscellaneous */
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Offset (0x00),
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OSYS, 16, // 0x00 - Operating System
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SMIF, 8, // 0x02 - SMI function
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PRM0, 8, // 0x03 - SMI function parameter
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PRM1, 8, // 0x04 - SMI function parameter
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SCIF, 8, // 0x05 - SCI function
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PRM2, 8, // 0x06 - SCI function parameter
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PRM3, 8, // 0x07 - SCI function parameter
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LCKF, 8, // 0x08 - Global Lock function for EC
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PRM4, 8, // 0x09 - Lock function parameter
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PRM5, 8, // 0x0a - Lock function parameter
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PCNT, 8, // 0x0b - Processor Count
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PPCM, 8, // 0x0c - Max PPC State
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TMPS, 8, // 0x0d - Temperature Sensor ID
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TLVL, 8, // 0x0e - Throttle Level Limit
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FLVL, 8, // 0x0f - Current FAN Level
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TCRT, 8, // 0x10 - Critical Threshold
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TPSV, 8, // 0x11 - Passive Threshold
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TMAX, 8, // 0x12 - CPU Tj_max
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S5U0, 8, // 0x13 - Enable USB in S5
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S3U0, 8, // 0x14 - Enable USB in S3
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S33G, 8, // 0x15 - Enable 3G in S3
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LIDS, 8, // 0x16 - LID State
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PWRS, 8, // 0x17 - AC Power State
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CMEM, 32, // 0x18 - 0x1b - CBMEM TOC
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CBMC, 32, // 0x1c - 0x1f - Coreboot Memory Console
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PM1I, 64, // 0x20 - 0x27 - PM1 wake status bit
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GPEI, 64, // 0x28 - 0x2f - GPE wake status bit
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DPTE, 8, // 0x30 - Enable DPTF
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NHLA, 64, // 0x31 - NHLT Address
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NHLL, 32, // 0x39 - NHLT Length
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CID1, 16, // 0x3d - Wifi Country Identifier
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U2WE, 16, // 0x3f - USB2 Wake Enable Bitmap
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U3WE, 8, // 0x41 - USB3 Wake Enable Bitmap
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/* ChromeOS specific */
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Offset (0x100),
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#include <vendorcode/google/chromeos/acpi/gnvs.asl>
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}
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/* Set flag to enable USB charging in S3 */
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Method (S3UE)
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{
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Store (One, \S3U0)
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}
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/* Set flag to disable USB charging in S3 */
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Method (S3UD)
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{
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Store (Zero, \S3U0)
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}
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/* Set flag to enable USB charging in S5 */
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Method (S5UE)
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{
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Store (One, \S5U0)
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}
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/* Set flag to disable USB charging in S5 */
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Method (S5UD)
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{
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Store (Zero, \S5U0)
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}
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