mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
85836c2215
The romstage component of Super I/O support is in fact written around
passing a lower and upper half packed integer. We currently have two
typedef's for this, 'device_t' and 'pnp_devfn_t'. We wish to make use of
'pnp_devfn_t' over 'device_t' as 'device_t' changes it's typedef in the
ramstage context and so is really a conflicting definition. This helps
solve problems down the road to having the 'real' 'device_t' definition
usable in romstage later.
This follows on from the rational given in:
c2956e7 device/pci_early.c: Mixes up variants of a typedefs to 'u32'
Change-Id: Ia9f238ebb944f9fe7b274621ee0c09a6de288a76
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6231
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins)
53 lines
1.6 KiB
C
53 lines
1.6 KiB
C
/*
|
|
* This file is part of the coreboot project.
|
|
*
|
|
* Copyright (C) 2005 Digital Design Corporation
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License as published by
|
|
* the Free Software Foundation; either version 2 of the License, or
|
|
* (at your option) any later version.
|
|
*
|
|
* This program is distributed in the hope that it will be useful,
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
* GNU General Public License for more details.
|
|
*
|
|
* You should have received a copy of the GNU General Public License
|
|
* along with this program; if not, write to the Free Software
|
|
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
|
*/
|
|
|
|
/* Pre-RAM driver for SMSC LPC47B272 Super I/O chip. */
|
|
|
|
#include <arch/io.h>
|
|
#include "lpc47b272.h"
|
|
|
|
static void pnp_enter_conf_state(pnp_devfn_t dev)
|
|
{
|
|
u16 port = dev >> 8;
|
|
outb(0x55, port);
|
|
}
|
|
|
|
static void pnp_exit_conf_state(pnp_devfn_t dev)
|
|
{
|
|
u16 port = dev >> 8;
|
|
outb(0xaa, port);
|
|
}
|
|
|
|
/**
|
|
* Configure the base I/O port of the specified serial device and enable the
|
|
* serial device.
|
|
*
|
|
* @param dev High 8 bits = Super I/O port, low 8 bits = logical device number.
|
|
* @param iobase Processor I/O port address to assign to this serial device.
|
|
*/
|
|
static void lpc47b272_enable_serial(pnp_devfn_t dev, u16 iobase)
|
|
{
|
|
pnp_enter_conf_state(dev);
|
|
pnp_set_logical_device(dev);
|
|
pnp_set_enable(dev, 0);
|
|
pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
|
|
pnp_set_enable(dev, 1);
|
|
pnp_exit_conf_state(dev);
|
|
}
|