mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
82cb93f6be
SPI read speed directly impacts boot time and we do quite a lot of reading. Add a way to easily find out the speed of SPI flash reads within coreboot. Write speed is less important since there are very few writes and they are small. BUG=chrome-os-partner:56556 BRANCH=none TEST=run on gru with SPI_SPEED_DEBUG set to 1. See the output messages: read SPI 627d4 7d73: 18455 us, 1740 KB/s, 13.920 Mbps Change-Id: Iec66f5b8e3ad62f14d836a538dc7801e4ca669e7 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/376944 Commit-Ready: Julius Werner <jwerner@chromium.org> Tested-by: Simon Glass <sjg@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
135 lines
3.5 KiB
C
135 lines
3.5 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright 2014 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/*
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* This file provides a common CBFS wrapper for SPI storage. SPI driver
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* context is expanded with the buffer descriptor used to store data read from
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* SPI.
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*/
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#include <boot_device.h>
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#include <spi_flash.h>
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#include <symbols.h>
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#include <cbmem.h>
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#include <timer.h>
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static struct spi_flash *spi_flash_info;
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/*
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* Set this to 1 to debug SPI speed, 0 to disable it
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* The format is:
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*
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* read SPI 62854 7db7: 10416 us, 3089 KB/s, 24.712 Mbps
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*
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* The important number is the last one. It should roughyly match your SPI
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* clock. If it doesn't, your driver might need a little tuning.
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*/
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#define SPI_SPEED_DEBUG 0
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static ssize_t spi_readat(const struct region_device *rd, void *b,
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size_t offset, size_t size)
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{
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struct stopwatch sw;
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bool show = SPI_SPEED_DEBUG && size >= 4*KiB;
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if (show)
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stopwatch_init(&sw);
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if (spi_flash_info->read(spi_flash_info, offset, size, b))
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return -1;
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if (show) {
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long usecs;
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usecs = stopwatch_duration_usecs(&sw);
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u64 speed; /* KiB/s */
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int bps; /* Bits per second */
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speed = (u64)size * 1000 / usecs;
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bps = speed * 8;
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printk(BIOS_DEBUG, "read SPI %#zx %#zx: %ld us, %lld KB/s, %d.%03d Mbps\n",
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offset, size, usecs, speed, bps / 1000, bps % 1000);
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}
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return size;
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}
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static ssize_t spi_writeat(const struct region_device *rd, const void *b,
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size_t offset, size_t size)
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{
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if (spi_flash_info->write(spi_flash_info, offset, size, b))
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return -1;
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return size;
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}
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static ssize_t spi_eraseat(const struct region_device *rd,
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size_t offset, size_t size)
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{
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if (spi_flash_info->erase(spi_flash_info, offset, size))
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return -1;
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return size;
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}
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/* Provide all operations on the same device. */
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static const struct region_device_ops spi_ops = {
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.mmap = mmap_helper_rdev_mmap,
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.munmap = mmap_helper_rdev_munmap,
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.readat = spi_readat,
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.writeat = spi_writeat,
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.eraseat = spi_eraseat,
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};
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static struct mmap_helper_region_device mdev =
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MMAP_HELPER_REGION_INIT(&spi_ops, 0, CONFIG_ROM_SIZE);
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static void switch_to_postram_cache(int unused)
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{
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/*
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* Call boot_device_init() to ensure spi_flash is initialized before
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* backing mdev with postram cache. This prevents the mdev backing from
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* being overwritten if spi_flash was not accessed before dram was up.
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*/
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boot_device_init();
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if (_preram_cbfs_cache != _postram_cbfs_cache)
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mmap_helper_device_init(&mdev, _postram_cbfs_cache,
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_postram_cbfs_cache_size);
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}
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ROMSTAGE_CBMEM_INIT_HOOK(switch_to_postram_cache);
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void boot_device_init(void)
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{
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int bus = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS;
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int cs = 0;
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if (spi_flash_info != NULL)
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return;
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spi_flash_info = spi_flash_probe(bus, cs);
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mmap_helper_device_init(&mdev, _cbfs_cache, _cbfs_cache_size);
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}
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/* Return the CBFS boot device. */
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const struct region_device *boot_device_ro(void)
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{
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if (spi_flash_info == NULL)
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return NULL;
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return &mdev.rdev;
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}
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/* The read-only and read-write implementations are symmetric. */
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const struct region_device *boot_device_rw(void)
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{
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return boot_device_ro();
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}
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