mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
80358a1f47
This reverts commit 399c022a8c.
This was merged too early. I'll repost it.
Change-Id: Iabac0aaa0a16404c885875137cf34bf64bf956f7
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20686
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
66 lines
2.4 KiB
Makefile
66 lines
2.4 KiB
Makefile
#
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# This file is part of the coreboot project.
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#
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# Copyright (C) 2015-2016 Intel Corp.
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; version 2 of the License.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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ifeq ($(CONFIG_PLATFORM_USES_FSP2_0),y)
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romstage-y += debug.c
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romstage-y += hand_off_block.c
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romstage-$(CONFIG_DISPLAY_FSP_HEADER) += header_display.c
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romstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c
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romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c
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romstage-$(CONFIG_VERIFY_HOBS) += hob_verify.c
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romstage-y += util.c
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romstage-y += memory_init.c
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romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
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romstage-$(CONFIG_MMA) += mma_core.c
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ramstage-y += debug.c
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ramstage-$(CONFIG_RUN_FSP_GOP) += graphics.c
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ramstage-y += hand_off_block.c
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ramstage-$(CONFIG_DISPLAY_FSP_HEADER) += header_display.c
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ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c
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ramstage-$(CONFIG_VERIFY_HOBS) += hob_verify.c
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ramstage-y += notify.c
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ramstage-y += silicon_init.c
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ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
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ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c
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ramstage-y += util.c
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ramstage-$(CONFIG_MMA) += mma_core.c
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postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
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postcar-$(CONFIG_FSP_CAR) += temp_ram_exit.c
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postcar-$(CONFIG_FSP_CAR) += util.c
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postcar-$(CONFIG_DISPLAY_FSP_HEADER) += header_display.c
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CPPFLAGS_common += -I$(src)/drivers/intel/fsp2_0/include
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# Add FSP blobs into cbfs. SoC code may supply additional options with
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# -options, e.g --xip or -b
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cbfs-files-$(CONFIG_FSP_CAR) += $(CONFIG_FSP_T_CBFS)
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$(CONFIG_FSP_T_CBFS)-file := $(call strip_quotes,$(CONFIG_FSP_T_FILE))
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$(CONFIG_FSP_T_CBFS)-type := fsp
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cbfs-files-$(CONFIG_ADD_FSP_BINARIES) += $(CONFIG_FSP_M_CBFS)
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$(CONFIG_FSP_M_CBFS)-file := $(call strip_quotes,$(CONFIG_FSP_M_FILE))
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$(CONFIG_FSP_M_CBFS)-type := fsp
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ifeq ($(CONFIG_FSP_M_XIP),y)
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$(CONFIG_FSP_M_CBFS)-options := --xip
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endif
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cbfs-files-$(CONFIG_ADD_FSP_BINARIES) += $(CONFIG_FSP_S_CBFS)
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$(CONFIG_FSP_S_CBFS)-file := $(call strip_quotes,$(CONFIG_FSP_S_FILE))
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$(CONFIG_FSP_S_CBFS)-type := fsp
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endif
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