mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
31 lines
483 B
C
31 lines
483 B
C
/* 32 bit mode code */
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#define PCI_COMMAND_PORT 0xcf8
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#define PCI_DATA_PORT 0xcfc
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#define NORTH_BRIDGE_BASE_ADDR 0x80000000
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#define LPC_BRIDGE_BASE_ADDR 0x80000800
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#define SMB_BASE_ADDR 0x5080
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#define RET_LABEL(label) \
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jmp label##_done
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#define CALL_LABEL(label) \
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jmp label ;\
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label##_done:
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#define CALL_SP(func) \
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leal 0f, %esp ; \
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jmp func ; \
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0:
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#define RET_SP \
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jmpl *%esp
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#define CALL_BP(func) \
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leal 0f, %ebp ; \
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jmp func ; \
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0:
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#define RET_BP \
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jmpl *%ebp
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