mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
This is the very very minimum needed to compile the code. Change-Id: I7f9e5f564181071591a4640019f59f91a4c456c6 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/13297 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
11 lines
125 B
C
11 lines
125 B
C
#include <cbmem.h>
|
|
#include <cpu/x86/smm.h>
|
|
|
|
void *cbmem_top(void)
|
|
{
|
|
return NULL;
|
|
}
|
|
|
|
void southbridge_smi_set_eos(void)
|
|
{
|
|
}
|