mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
7e78ce492a
The option code is tricky as it is used by standalone code. If you include that file and you are standalone, you now have to define STANDALONE (is there a better way?) Change the cpuid to be a 24-byte string instead of 3 u32s. Make the CPUID usage PIC-safe by not using %ebx. Test building on two different geodes, tested to boot on dbe62 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://coreboot.org/repository/coreboot-v3@750 f3766cd6-281f-0410-b1cd-43a5c92072e9
131 lines
4.2 KiB
C
131 lines
4.2 KiB
C
/*
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* Copyright (C) 200X FIXME
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* Copyright (C) 2007 coresystems GmbH
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* Copyright (C) 2007 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
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*
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*/
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#ifndef MC146818RTC_H
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#define MC146818RTC_H
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#ifndef RTC_BASE_PORT
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#define RTC_BASE_PORT 0x70
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#endif
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#define RTC_PORT(x) (RTC_BASE_PORT + (x))
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/* control registers - Moto names
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*/
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#define RTC_REG_A 10
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#define RTC_REG_B 11
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#define RTC_REG_C 12
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#define RTC_REG_D 13
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/**********************************************************************
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* register details
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**********************************************************************/
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#define RTC_FREQ_SELECT RTC_REG_A
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/* update-in-progress - set to "1" 244 microsecs before RTC goes off the bus,
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* reset after update (may take 1.984ms @ 32768Hz RefClock) is complete,
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* totalling to a max high interval of 2.228 ms.
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*/
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# define RTC_UIP 0x80
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# define RTC_DIV_CTL 0x70
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/* divider control: refclock values 4.194 / 1.049 MHz / 32.768 kHz */
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# define RTC_REF_CLCK_4MHZ 0x00
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# define RTC_REF_CLCK_1MHZ 0x10
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# define RTC_REF_CLCK_32KHZ 0x20
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/* 2 values for divider stage reset, others for "testing purposes only" */
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# define RTC_DIV_RESET1 0x60
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# define RTC_DIV_RESET2 0x70
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/* Periodic intr. / Square wave rate select. 0=none, 1=32.8kHz,... 15=2Hz */
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# define RTC_RATE_SELECT 0x0F
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# define RTC_RATE_NONE 0x00
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# define RTC_RATE_32786HZ 0x01
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# define RTC_RATE_16384HZ 0x02
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# define RTC_RATE_8192HZ 0x03
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# define RTC_RATE_4096HZ 0x04
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# define RTC_RATE_2048HZ 0x05
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# define RTC_RATE_1024HZ 0x06
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# define RTC_RATE_512HZ 0x07
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# define RTC_RATE_256HZ 0x08
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# define RTC_RATE_128HZ 0x09
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# define RTC_RATE_64HZ 0x0a
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# define RTC_RATE_32HZ 0x0b
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# define RTC_RATE_16HZ 0x0c
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# define RTC_RATE_8HZ 0x0d
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# define RTC_RATE_4HZ 0x0e
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# define RTC_RATE_2HZ 0x0f
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/**********************************************************************/
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#define RTC_CONTROL RTC_REG_B
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# define RTC_SET 0x80 /* disable updates for clock setting */
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# define RTC_PIE 0x40 /* periodic interrupt enable */
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# define RTC_AIE 0x20 /* alarm interrupt enable */
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# define RTC_UIE 0x10 /* update-finished interrupt enable */
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# define RTC_SQWE 0x08 /* enable square-wave output */
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# define RTC_DM_BINARY 0x04 /* all time/date values are BCD if clear */
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# define RTC_24H 0x02 /* 24 hour mode - else hours bit 7 means pm */
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# define RTC_DST_EN 0x01 /* auto switch DST - works f. USA only */
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/**********************************************************************/
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#define RTC_INTR_FLAGS RTC_REG_C
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/* caution - cleared by read */
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# define RTC_IRQF 0x80 /* any of the following 3 is active */
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# define RTC_PF 0x40
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# define RTC_AF 0x20
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# define RTC_UF 0x10
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/**********************************************************************/
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#define RTC_VALID RTC_REG_D
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# define RTC_VRT 0x80 /* valid RAM and time */
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/**********************************************************************/
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/* On PCs, the checksum is built only over bytes 16..45 */
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#define PC_CKS_RANGE_START 16
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#define PC_CKS_RANGE_END 45
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#define PC_CKS_LOC 46
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/* coreboot checksum is built only over bytes 49..125 */
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#ifndef CB_CKS_RANGE_START
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#define CB_CKS_RANGE_START 49
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#endif
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#ifndef CB_CKS_RANGE_END
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#define CB_CKS_RANGE_END 125
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#endif
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#ifndef CB_CKS_LOC
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#define CB_CKS_LOC 126
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#endif
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#define RTC_BOOT_BYTE 48
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#define RTC_BOOT_COUNT_SHIFT 4
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#define RTC_LAST_BOOT_FLAG_SET (1<<1)
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#define RTC_NORMAL_BOOT_FLAG_SET (1<<0)
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#ifdef STANDALONE /* standalone program using this file */
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int get_option(void *dest, char *name);
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#else
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#include <shared.h>
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SHARED(get_option, int, void *dest, char *name);
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#endif
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void rtc_init(int invalid);
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int last_boot_normal(void);
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int check_normal_boot_flag(void);
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#endif /* MC146818RTC_H */
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