mirror of
https://github.com/fail0verflow/switch-coreboot.git
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0528863e20
southbridge drivers in Kconfig. * It includes initial superio code as well, but there is at least one error in the pnp_device.c/superio scenario left * Fixed biosemu.c, vm86.c, pnp_device.c (sort of) * Enable vm86 instead of x86emu per default for vga init for now. This makes VGA in qemu work. There might be a bug in x86emu or the compiler I am using. (gcc version 4.1.2 20070115 (prerelease) (SUSE Linux)) * Import isa-dma.c, keyboard.c and i8259.c from v2 /pc80, which was taken from LinuxBIOSv1 released from LANL under release LA-CC Number 00-34 and using parts from the Linux kernel. This patch makes vga and keyboard work in qemu. Yippie Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@260 f3766cd6-281f-0410-b1cd-43a5c92072e9
44 lines
1.8 KiB
C
44 lines
1.8 KiB
C
#include <arch/io.h>
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#include <isa-dma.h>
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/* DMA controller registers */
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#define DMA1_CMD_REG 0x08 /* command register (w) */
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#define DMA1_STAT_REG 0x08 /* status register (r) */
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#define DMA1_REQ_REG 0x09 /* request register (w) */
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#define DMA1_MASK_REG 0x0A /* single-channel mask (w) */
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#define DMA1_MODE_REG 0x0B /* mode register (w) */
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#define DMA1_CLEAR_FF_REG 0x0C /* clear pointer flip-flop (w) */
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#define DMA1_TEMP_REG 0x0D /* Temporary Register (r) */
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#define DMA1_RESET_REG 0x0D /* Master Clear (w) */
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#define DMA1_CLR_MASK_REG 0x0E /* Clear Mask */
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#define DMA1_MASK_ALL_REG 0x0F /* all-channels mask (w) */
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#define DMA2_CMD_REG 0xD0 /* command register (w) */
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#define DMA2_STAT_REG 0xD0 /* status register (r) */
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#define DMA2_REQ_REG 0xD2 /* request register (w) */
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#define DMA2_MASK_REG 0xD4 /* single-channel mask (w) */
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#define DMA2_MODE_REG 0xD6 /* mode register (w) */
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#define DMA2_CLEAR_FF_REG 0xD8 /* clear pointer flip-flop (w) */
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#define DMA2_TEMP_REG 0xDA /* Temporary Register (r) */
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#define DMA2_RESET_REG 0xDA /* Master Clear (w) */
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#define DMA2_CLR_MASK_REG 0xDC /* Clear Mask */
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#define DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */
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#define DMA_MODE_READ 0x44 /* I/O to memory, no autoinit, increment, single mode */
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#define DMA_MODE_WRITE 0x48 /* memory to I/O, no autoinit, increment, single mode */
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#define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */
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#define DMA_AUTOINIT 0x10
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void isa_dma_init(void)
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{
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/* slave at 0x00 - 0x0f */
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/* master at 0xc0 - 0xdf */
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/* 0x80 - 0x8f DMA page registers */
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/* DMA: 0x00, 0x02, 0x4, 0x06 base address for DMA channel */
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outb(0, DMA1_RESET_REG);
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outb(0, DMA2_RESET_REG);
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outb(DMA_MODE_CASCADE, DMA2_MODE_REG);
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outb(0, DMA2_MASK_REG);
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}
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