mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
784450567f
Geode still builds fine. include/lib.h includes a new function, cycles(), which is a u64 and architecture-defined. (Thanks, Plan 9, for a sensible idea). All rdtsc removed in favor of cycles() All other changes are k8 specific. None of these changes adversely impact existing platforms AFAICT. Goal is that by 31/8/8, we're testing on simnow. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://coreboot.org/repository/coreboot-v3@807 f3766cd6-281f-0410-b1cd-43a5c92072e9
262 lines
7.7 KiB
C
262 lines
7.7 KiB
C
/*
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* K8 northbridge
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* This file is part of the coreboot project.
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* Copyright (C) 2004-2005 Linux Networx
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* (Written by Eric Biederman <ebiederman@lnxi.com> and Jason Schildt for Linux Networx)
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* Copyright (C) 2005-7 YingHai Lu
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* Copyright (C) 2005 Ollie Lo
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* Copyright (C) 2005-2007 Stefan Reinauer <stepan@openbios.org>
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* Copyright (C) 2008 Ronald G. Minnich <rminnich@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
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*/
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/* This should be done by Eric
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2004.12 yhlu add dual core support
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2005.01 yhlu add support move apic before pci_domain in MB Config.lb
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2005.02 yhlu add e0 memory hole support
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2005.11 yhlu add put sb ht chain on bus 0
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*/
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#include <console.h>
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#include <lib.h>
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#include <string.h>
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#include <mtrr.h>
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#include <macros.h>
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#include <spd.h>
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#include <cpu.h>
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#include <msr.h>
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#include <amd/k8/k8.h>
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#include <amd/k8/sysconf.h>
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#include <device/pci.h>
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#include <device/hypertransport_def.h>
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#include <device/hypertransport.h>
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#include <mc146818rtc.h>
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#include <lib.h>
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#include <lapic.h>
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/*
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#if CONFIG_HW_MEM_HOLE_SIZEK != 0
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#include <cpu/amd/model_fxx_rev.h>
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#endif
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*/
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struct amdk8_sysconf sysconf;
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#define FX_DEVS 8
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struct device * __f0_dev[FX_DEVS];
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struct device * __f1_dev[FX_DEVS];
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#if 0
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void debug_fx_devs(void)
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{
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int i;
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for(i = 0; i < FX_DEVS; i++) {
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struct device * dev;
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dev = __f0_dev[i];
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if (dev) {
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printk(BIOS_DEBUG, "__f0_dev[%d]: %s bus: %p\n",
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i, dev_path(dev), dev->bus);
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}
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dev = __f1_dev[i];
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if (dev) {
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printk(BIOS_DEBUG, "__f1_dev[%d]: %s bus: %p\n",
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i, dev_path(dev), dev->bus);
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}
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}
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}
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#endif
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void get_fx_devs(void)
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{
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int i;
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if (__f1_dev[0]) {
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return;
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}
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for(i = 0; i < FX_DEVS; i++) {
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__f0_dev[i] = dev_find_slot(0, PCI_DEVFN(0x18 + i, 0));
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__f1_dev[i] = dev_find_slot(0, PCI_DEVFN(0x18 + i, 1));
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}
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if (!__f1_dev[0]) {
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die("Cannot find 0:0x18.1\n");
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}
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}
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u32 f1_read_config32(unsigned int reg)
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{
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get_fx_devs();
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return pci_read_config32(__f1_dev[0], reg);
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}
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void f1_write_config32(unsigned int reg, u32 value)
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{
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int i;
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get_fx_devs();
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for(i = 0; i < FX_DEVS; i++) {
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struct device * dev;
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dev = __f1_dev[i];
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if (dev && dev->enabled) {
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pci_write_config32(dev, reg, value);
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}
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}
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}
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unsigned int amdk8_nodeid(struct device * dev)
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{
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return (dev->path.pci.devfn >> 3) - 0x18;
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}
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#if CONFIG_HW_MEM_HOLE_SIZEK != 0
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struct hw_mem_hole_info get_hw_mem_hole_info(void)
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{
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struct hw_mem_hole_info mem_hole;
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int i;
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mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK;
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mem_hole.node_id = -1;
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for (i = 0; i < 8; i++) {
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u32 base;
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u32 hole;
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base = f1_read_config32(0x40 + (i << 3));
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if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
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continue;
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}
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hole = pci_read_config32(__f1_dev[i], 0xf0);
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if(hole & 1) { // we find the hole
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mem_hole.hole_startk = (hole & (0xff<<24)) >> 10;
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mem_hole.node_id = i; // record the node No with hole
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break; // only one hole
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}
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}
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//We need to double check if there is speical set on base reg and limit reg are not continous instead of hole, it will find out it's hole_startk
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if(mem_hole.node_id==-1) {
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u32 limitk_pri = 0;
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for(i=0; i<8; i++) {
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u32 base, limit;
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unsigned base_k, limit_k;
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base = f1_read_config32(0x40 + (i << 3));
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if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
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continue;
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}
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base_k = (base & 0xffff0000) >> 2;
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if(limitk_pri != base_k) { // we find the hole
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mem_hole.hole_startk = limitk_pri;
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mem_hole.node_id = i;
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break; //only one hole
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}
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limit = f1_read_config32(0x44 + (i << 3));
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limit_k = ((limit + 0x00010000) & 0xffff0000) >> 2;
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limitk_pri = limit_k;
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}
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}
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return mem_hole;
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}
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void disable_hoist_memory(unsigned long hole_startk, int i)
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{
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int ii;
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struct device * dev;
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u32 base, limit;
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u32 hoist;
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u32 hole_sizek;
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//1. find which node has hole
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//2. change limit in that node.
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//3. change base and limit in later node
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//4. clear that node f0
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//if there is not mem hole enabled, we need to change it's base instead
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hole_sizek = (4*1024*1024) - hole_startk;
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for(ii=7;ii>i;ii--) {
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base = f1_read_config32(0x40 + (ii << 3));
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if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
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continue;
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}
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limit = f1_read_config32(0x44 + (ii << 3));
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f1_write_config32(0x44 + (ii << 3),limit - (hole_sizek << 2));
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f1_write_config32(0x40 + (ii << 3),base - (hole_sizek << 2));
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}
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limit = f1_read_config32(0x44 + (i << 3));
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f1_write_config32(0x44 + (i << 3),limit - (hole_sizek << 2));
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dev = __f1_dev[i];
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hoist = pci_read_config32(dev, 0xf0);
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if(hoist & 1) {
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pci_write_config32(dev, 0xf0, 0);
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}
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else {
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base = pci_read_config32(dev, 0x40 + (i << 3));
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f1_write_config32(0x40 + (i << 3),base - (hole_sizek << 2));
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}
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}
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u32 hoist_memory(unsigned long hole_startk, int i)
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{
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int ii;
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u32 carry_over;
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struct device * dev;
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u32 base, limit;
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u32 basek;
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u32 hoist;
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carry_over = (4*1024*1024) - hole_startk;
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for(ii=7;ii>i;ii--) {
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base = f1_read_config32(0x40 + (ii << 3));
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if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
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continue;
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}
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limit = f1_read_config32(0x44 + (ii << 3));
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f1_write_config32(0x44 + (ii << 3),limit + (carry_over << 2));
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f1_write_config32(0x40 + (ii << 3),base + (carry_over << 2));
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}
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limit = f1_read_config32(0x44 + (i << 3));
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f1_write_config32(0x44 + (i << 3),limit + (carry_over << 2));
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dev = __f1_dev[i];
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base = pci_read_config32(dev, 0x40 + (i << 3));
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basek = (base & 0xffff0000) >> 2;
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if(basek == hole_startk) {
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//don't need set memhole here, because hole off set will be 0, overflow
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//so need to change base reg instead, new basek will be 4*1024*1024
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base &= 0x0000ffff;
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base |= (4*1024*1024)<<2;
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f1_write_config32(0x40 + (i<<3), base);
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}
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else
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{
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hoist = /* hole start address */
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((hole_startk << 10) & 0xff000000) +
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/* hole address to memory controller address */
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(((basek + carry_over) >> 6) & 0x0000ff00) +
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/* enable */
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1;
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pci_write_config32(dev, 0xf0, hoist);
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}
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return carry_over;
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}
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#endif
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