mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
76d17719fe
Add global/ACPI nvs variables required for IGD OpRegion. Add functions necessary to save the ACPI OpRegion table address in ASLB, and restore table address upon S3 resume. Implementation modeled on existing Baytrail code. Test: boot Windows 10 on google/chell with Tianocore payload and GOP display init, observe display driver loaded and functional, display not black screen when resuming from S3 suspend. Change-Id: Icd6b514e531eec6e49dbb03eb765144f41c1e31b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/25198 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
143 lines
4.5 KiB
Text
143 lines
4.5 KiB
Text
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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* Copyright (C) 2014 Google Inc.
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* Copyright (C) 2015 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/* Global Variables */
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Name (\PICM, 0) // IOAPIC/8259
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/*
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* Global ACPI memory region. This region is used for passing information
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* between coreboot (aka "the system bios"), ACPI, and the SMI handler.
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* Since we don't know where this will end up in memory at ACPI compile time,
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* we have to fix it up in coreboot's ACPI creation phase.
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*/
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External (NVSA)
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OperationRegion (GNVS, SystemMemory, NVSA, 0x2000)
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Field (GNVS, ByteAcc, NoLock, Preserve)
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{
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/* Miscellaneous */
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Offset (0x00),
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OSYS, 16, // 0x00 - Operating System
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SMIF, 8, // 0x02 - SMI function
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PRM0, 8, // 0x03 - SMI function parameter
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PRM1, 8, // 0x04 - SMI function parameter
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SCIF, 8, // 0x05 - SCI function
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PRM2, 8, // 0x06 - SCI function parameter
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PRM3, 8, // 0x07 - SCI function parameter
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LCKF, 8, // 0x08 - Global Lock function for EC
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PRM4, 8, // 0x09 - Lock function parameter
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PRM5, 8, // 0x0a - Lock function parameter
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PCNT, 8, // 0x0b - Processor Count
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PPCM, 8, // 0x0c - Max PPC State
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TMPS, 8, // 0x0d - Temperature Sensor ID
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TLVL, 8, // 0x0e - Throttle Level Limit
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FLVL, 8, // 0x0f - Current FAN Level
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TCRT, 8, // 0x10 - Critical Threshold
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TPSV, 8, // 0x11 - Passive Threshold
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TMAX, 8, // 0x12 - CPU Tj_max
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S5U0, 8, // 0x13 - Enable USB in S5
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S3U0, 8, // 0x14 - Enable USB in S3
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S33G, 8, // 0x15 - Enable 3G in S3
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LIDS, 8, // 0x16 - LID State
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PWRS, 8, // 0x17 - AC Power State
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CMEM, 32, // 0x18 - 0x1b - CBMEM TOC
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CBMC, 32, // 0x1c - 0x1f - coreboot Memory Console
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PM1I, 64, // 0x20 - 0x27 - PM1 wake status bit
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GPEI, 64, // 0x28 - 0x2f - GPE wake status bit
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DPTE, 8, // 0x30 - Enable DPTF
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NHLA, 64, // 0x31 - NHLT Address
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NHLL, 32, // 0x39 - NHLT Length
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CID1, 16, // 0x3d - Wifi Country Identifier
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U2WE, 16, // 0x3f - USB2 Wake Enable Bitmap
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U3WE, 8, // 0x41 - USB3 Wake Enable Bitmap
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UIOR, 8, // 0x42 - UART debug controller init on S3 resume
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EPCS, 8, // 0x43 - SGX Enabled status
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EMNA, 64, // 0x44 - 0x4B EPC base address
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ELNG, 64, // 0x4C - 0x53 EPC Length
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/* IGD OpRegion */
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Offset (0xb4),
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ASLB, 32, // 0xb4 - IGD OpRegion Base Address
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IBTT, 8, // 0xb8 - IGD boot panel device
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IPAT, 8, // 0xb9 - IGD panel type cmos option
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ITVF, 8, // 0xba - IGD TV format cmos option
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ITVM, 8, // 0xbb - IGD TV minor format option
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IPSC, 8, // 0xbc - IGD panel scaling
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IBLC, 8, // 0xbd - IGD BLC config
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IBIA, 8, // 0xbe - IGD BIA config
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ISSC, 8, // 0xbf - IGD SSC config
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I409, 8, // 0xc0 - IGD 0409 modified settings
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I509, 8, // 0xc1 - IGD 0509 modified settings
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I609, 8, // 0xc2 - IGD 0609 modified settings
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I709, 8, // 0xc3 - IGD 0709 modified settings
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IDMM, 8, // 0xc4 - IGD Power conservation feature
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IDMS, 8, // 0xc5 - IGD DVMT memory size
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IF1E, 8, // 0xc6 - IGD function 1 enable
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HVCO, 8, // 0xc7 - IGD HPLL VCO
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NXD1, 32, // 0xc8 - IGD _DGS next DID1
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NXD2, 32, // 0xcc - IGD _DGS next DID2
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NXD3, 32, // 0xd0 - IGD _DGS next DID3
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NXD4, 32, // 0xd4 - IGD _DGS next DID4
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NXD5, 32, // 0xd8 - IGD _DGS next DID5
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NXD6, 32, // 0xdc - IGD _DGS next DID6
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NXD7, 32, // 0xe0 - IGD _DGS next DID7
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NXD8, 32, // 0xe4 - IGD _DGS next DID8
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ISCI, 8, // 0xe8 - IGD SMI/SCI mode (0: SCI)
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PAVP, 8, // 0xe9 - IGD PAVP data
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Offset (0xeb),
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OSCC, 8, // 0xeb - PCIe OSC control
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NPCE, 8, // 0xec - native pcie support
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PLFL, 8, // 0xed - platform flavor
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BREV, 8, // 0xee - board revision
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DPBM, 8, // 0xef - digital port b mode
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DPCM, 8, // 0xf0 - digital port c mode
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DPDM, 8, // 0xf1 - digital port d mode
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ALFP, 8, // 0xf2 - active lfp
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IMON, 8, // 0xf3 - current graphics turbo imon value
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MMIO, 8, // 0xf4 - 64bit mmio support
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/* ChromeOS specific */
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Offset (0x100),
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#include <vendorcode/google/chromeos/acpi/gnvs.asl>
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}
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/* Set flag to enable USB charging in S3 */
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Method (S3UE)
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{
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Store (One, \S3U0)
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}
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/* Set flag to disable USB charging in S3 */
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Method (S3UD)
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{
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Store (Zero, \S3U0)
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}
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/* Set flag to enable USB charging in S5 */
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Method (S5UE)
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{
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Store (One, \S5U0)
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}
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/* Set flag to disable USB charging in S5 */
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Method (S5UD)
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{
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Store (Zero, \S5U0)
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}
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