mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
718dab6ba5
This includes: - the working power button patch. - onchipuart2 for very early startup -- this will be replaced with a better mechanism soon. - dts mod for powerbutton on cs5536 - dbe62 dts fix for COM1 setup - ram check call in dbe62 initram.c - Carl-Daniel's fix to detect incorrect access to spd variables. - more debug prints in geodelx northbridge support code. This is cumulative since we're lagging on acks a bit and it's hard to keep this stuff all seperated out since it involves a common set of files. I'd like to get it acked and in tree today if possible. It's a very small set of lines changed so please forgive me for the cumulative nature. Thanks Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://coreboot.org/repository/coreboot-v3@636 f3766cd6-281f-0410-b1cd-43a5c92072e9
159 lines
4.4 KiB
C
159 lines
4.4 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007 Advanced Micro Devices, Inc.
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* Copyright (C) 2007 Ronald G. Minnich
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#define _MAINOBJECT
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#include <types.h>
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#include <lib.h>
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#include <console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <string.h>
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#include <msr.h>
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#include <io.h>
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#include <amd_geodelx.h>
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#include <northbridge/amd/geodelx/raminit.h>
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#include <spd.h>
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#define MANUALCONF 0 /* Do automatic strapped PLL config */
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#define PLLMSRHI 0x00001490 /* manual settings for the PLL */
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#define PLLMSRLO 0x02000030
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#define DIMM0 ((u8) 0xA0)
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#define DIMM1 ((u8) 0xA2)
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/* The part is a Micron MT46V16M16 P 5B
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* 4 M x 16 x 5 Banks, 200 Mhz, Plastic package, TSOP, DDR400B, 5 ns CL3
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* Commercial rating.
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* @ 200 ns, data-out window, 1.6; access, +- 70 ns; dqs-dq skew: .4ns
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* http://www.micron.com/products/partdetail?part=MT46V16M16P-5B
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*/
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struct spd_entry {
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u8 address;
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u8 data;
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};
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/* Save space by using a short list of SPD values used by Geode LX Memory init */
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static const struct spd_entry spd_table[] = {
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{SPD_ACCEPTABLE_CAS_LATENCIES, 0xe},
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{SPD_BANK_DENSITY, 0x40},
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{SPD_DEVICE_ATTRIBUTES_GENERAL, 0xff},
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{SPD_MEMORY_TYPE, 7},
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{SPD_MIN_CYCLE_TIME_AT_CAS_MAX, 10}, /* A guess for the tRAC value */
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{SPD_MODULE_ATTRIBUTES, 0xff}, /* FIXME later when we figure out. */
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{SPD_NUM_BANKS_PER_SDRAM, 4},
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{SPD_PRIMARY_SDRAM_WIDTH, 8},
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{SPD_NUM_DIMM_BANKS, 1},
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{SPD_NUM_COLUMNS, 0xa},
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{SPD_NUM_ROWS, 13},
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{SPD_REFRESH, 0x3a},
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{SPD_SDRAM_CYCLE_TIME_2ND, 60},
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{SPD_SDRAM_CYCLE_TIME_3RD, 75},
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{SPD_tRAS, 40},
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{SPD_tRCD, 15},
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{SPD_tRFC, 70},
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{SPD_tRP, 15},
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{SPD_tRRD, 10},
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};
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/**
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* Given an SMBUS device, and an address in that device, return the value of SPD
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* for that device. In this mainboard, the only one that can return is DIMM0.
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* @param device The device number
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* @param address The address in SPD rom to return the value of
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* @returns The value
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*/
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u8 spd_read_byte(u16 device, u8 address)
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{
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int i;
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/* returns 0xFF on any failures */
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u8 ret = 0xff;
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printk(BIOS_DEBUG, "spd_read_byte dev %04x", device);
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if (device == DIMM0) {
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for (i = 0; i < ARRAY_SIZE(spd_table); i++) {
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if (spd_table[i].address == address) {
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ret = spd_table[i].data;
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break;
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}
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}
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if (i == ARRAY_SIZE(spd_table))
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printk(BIOS_DEBUG, " addr %02x does not exist in SPD table",
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address);
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}
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printk(BIOS_DEBUG, " addr %02x returns %02x\n", address, ret);
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return ret;
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}
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/**
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* Placeholder in case we ever need it. Since this file is a
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* template for other motherboards, we want this here and we want the
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* call in the right place.
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*/
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static void mb_gpio_init(void)
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{
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/* Early mainboard specific GPIO setup */
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}
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/**
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* main for initram for the PC Engines Alix 1C. It might seem that you
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* could somehow do these functions in, e.g., the cpu code, but the
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* order of operations and what those operations are is VERY strongly
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* mainboard dependent. It's best to leave it in the mainboard code.
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*/
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int main(void)
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{
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u8 smb_devices[] = {
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DIMM0, DIMM1
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};
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printk(BIOS_DEBUG, "Hi there from stage1\n");
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post_code(POST_START_OF_MAIN);
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system_preinit();
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printk(BIOS_DEBUG, "done preinit\n");
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mb_gpio_init();
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printk(BIOS_DEBUG, "done gpio init\n");
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pll_reset(MANUALCONF, PLLMSRHI, PLLMSRLO);
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printk(BIOS_DEBUG, "done pll reset\n");
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cpu_reg_init(0, DIMM0, DIMM1);
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printk(BIOS_DEBUG, "done cpu reg init\n");
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sdram_set_registers();
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printk(BIOS_DEBUG, "done sdram set registers\n");
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sdram_set_spd_registers(DIMM0, DIMM1);
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printk(BIOS_DEBUG, "done sdram set spd registers\n");
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sdram_enable(DIMM0, DIMM1);
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printk(BIOS_DEBUG, "done sdram enable\n");
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/* Check low memory */
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ram_check(0x00000000, 640*1024);
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printk(BIOS_DEBUG, "stage1 returns\n");
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return 0;
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}
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