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6fa4b6b19f
Change-Id: I71443c7547a113bf9b64d48fe5a85c6e2302c8aa Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/15208 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://chromium-review.googlesource.com/354981 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
31 lines
1 KiB
C
31 lines
1 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <soc/pei_data.h>
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#include <mainboard/google/rikku/spd/spd.h>
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/* Copy SPD data for on-board memory */
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void mainboard_fill_spd_data(struct pei_data *pei_data)
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{
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pei_data->spd_addresses[0] = 0xa0;
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pei_data->spd_addresses[1] = 0x00;
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pei_data->spd_addresses[2] = 0xa4;
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pei_data->spd_addresses[3] = 0x00;
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pei_data->dimm_channel0_disabled = 2;
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pei_data->dimm_channel1_disabled = 2;
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// Enable 2x refresh mode
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pei_data->ddr_refresh_2x = 1;
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pei_data->dq_pins_interleaved = 1;
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}
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