Emulation/switch-coreboot
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switch-coreboot/src
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Edward O'Callaghan 6d51f6b2e8 superio/fintek/*: Fix header style 
Remove some redundant includes. Fix repetitiveness in include guards and
strip some misplaced tabs for whitespaces.

Change-Id: I1f0bf6951cc6714f63e88b323754515fb02c089c
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5572
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-26 13:48:36 +02:00
..
arch Rename coreboot_ram stage to ramstage 2014-04-26 13:27:09 +02:00
console console: Simplify the enable rules 2014-04-18 16:41:09 +02:00
cpu Rename coreboot_ram stage to ramstage 2014-04-26 13:27:09 +02:00
device OxPCIe uart: Split PCI bridge control 2014-04-09 11:29:45 +02:00
drivers Get rid of HAVE_INIT_TIMER config option 2014-04-26 13:25:28 +02:00
ec ec/compal/ene932: Update to use coreboot EC-mainboard API 2014-04-19 03:49:48 +02:00
include Get rid of HAVE_INIT_TIMER config option 2014-04-26 13:25:28 +02:00
lib Rename coreboot_ram stage to ramstage 2014-04-26 13:27:09 +02:00
mainboard Rename coreboot_ram stage to ramstage 2014-04-26 13:27:09 +02:00
northbridge Rename coreboot_ram stage to ramstage 2014-04-26 13:27:09 +02:00
soc console: Move newline translation outside console_tx_byte 2014-04-09 13:21:25 +02:00
southbridge Rename coreboot_ram stage to ramstage 2014-04-26 13:27:09 +02:00
superio superio/fintek/*: Fix header style 2014-04-26 13:48:36 +02:00
vendorcode vendorcode/amd/agesa/fam14: Build as a static library 2014-04-15 17:23:37 +02:00
Kconfig Rename coreboot_ram stage to ramstage 2014-04-26 13:27:09 +02:00