mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
6a16f697d8
When warm booting, SD card reader on Tegra 124 needs to be reset by setting
power GPIO to zero. Since we don't really access SD card in Coreboot, set it to
zero and let payloads enable power when they need to access SD cards.
CQ-DEPEND=CL:196783
BRANCH=nyan
BUG=chrome-os-partner:27053
TEST=emerge-nyan coreboot depthcharge chromeos-bootimage
# With related changes in depthcharge, boots SD card successfully.
Original-Change-Id: I2d368eb9480c978e9e343648b58a729028c94622
Original-Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/196774
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: Andrew Bresticker <abrestic@chromium.org>
(cherry picked from commit 62bb7d04dff1a87474a8557f144b24e6b7d006ae)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I3429535d0d032f9db89d8e70a525a6281102537a
Reviewed-on: http://review.coreboot.org/7865
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
269 lines
8.9 KiB
C
269 lines
8.9 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright 2013 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <arch/io.h>
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#include <device/device.h>
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#include <elog.h>
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#include <boot/coreboot_tables.h>
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#include <soc/addressmap.h>
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#include <soc/clock.h>
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#include <soc/nvidia/tegra/i2c.h>
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#include <soc/nvidia/tegra124/clk_rst.h>
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#include <soc/nvidia/tegra124/gpio.h>
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#include <soc/nvidia/tegra124/mc.h>
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#include <soc/nvidia/tegra124/pmc.h>
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#include <soc/nvidia/tegra124/spi.h>
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#include <soc/nvidia/tegra124/usb.h>
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static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE;
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static void set_clock_sources(void)
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{
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/*
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* The max98090 codec and the temperature sensor are on I2C1. These
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* can both run at 400 KHz, but the kernel sets the bus to 100 KHz.
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*/
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clock_configure_i2c_scl_freq(i2c1, PLLP, 100);
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/*
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* MMC3 and MMC4: Set base clock frequency for SD Clock to Tegra MMC's
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* maximum speed (48MHz) so we can change SDCLK by second stage divisor
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* in payloads, without touching base clock.
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*/
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clock_configure_source(sdmmc3, PLLP, 48000);
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clock_configure_source(sdmmc4, PLLP, 48000);
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/* External peripheral 1: audio codec (max98090) using 12MHz CLK1.
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* Note the source id of CLK_M for EXTPERIPH1 is 3. */
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clock_configure_irregular_source(extperiph1, CLK_M, 12000, 3);
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/*
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* We need 1.5MHz. So, we use CLK_M. CLK_DIVIDER macro returns a divisor
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* (0xe) a little bit off from the ideal value (0xd) but it's good
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* enough for beeps. The source id of CLK_M for I2S is 6.
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*/
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clock_configure_irregular_source(i2s1, CLK_M, 1500, 6);
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/* Note source id of PLLP for HOST1x is 4. */
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clock_configure_irregular_source(host1x, PLLP, 408000, 4);
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/* Use PLLD_OUT0 as clock source for disp1 */
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clrsetbits_le32(&clk_rst->clk_src_disp1,
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CLK_SOURCE_MASK | CLK_DIVISOR_MASK,
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2 /*PLLD_OUT0 */ << CLK_SOURCE_SHIFT);
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}
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static void setup_pinmux(void)
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{
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// I2C1 clock.
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pinmux_set_config(PINMUX_GEN1_I2C_SCL_INDEX,
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PINMUX_GEN1_I2C_SCL_FUNC_I2C1 | PINMUX_INPUT_ENABLE);
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// I2C1 data.
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pinmux_set_config(PINMUX_GEN1_I2C_SDA_INDEX,
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PINMUX_GEN1_I2C_SDA_FUNC_I2C1 | PINMUX_INPUT_ENABLE);
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// I2C2 clock.
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pinmux_set_config(PINMUX_GEN2_I2C_SCL_INDEX,
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PINMUX_GEN2_I2C_SCL_FUNC_I2C2 | PINMUX_INPUT_ENABLE);
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// I2C2 data.
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pinmux_set_config(PINMUX_GEN2_I2C_SDA_INDEX,
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PINMUX_GEN2_I2C_SDA_FUNC_I2C2 | PINMUX_INPUT_ENABLE);
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// I2C4 (DDC) clock.
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pinmux_set_config(PINMUX_DDC_SCL_INDEX,
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PINMUX_DDC_SCL_FUNC_I2C4 | PINMUX_INPUT_ENABLE);
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// I2C4 (DDC) data.
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pinmux_set_config(PINMUX_DDC_SDA_INDEX,
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PINMUX_DDC_SDA_FUNC_I2C4 | PINMUX_INPUT_ENABLE);
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// TODO(hungte) Revice pinmux setup, make nice little SoC functions for
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// every single logical thing instead of dumping a wall of code below.
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uint32_t pin_up = PINMUX_PULL_UP | PINMUX_INPUT_ENABLE,
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pin_down = PINMUX_PULL_DOWN | PINMUX_INPUT_ENABLE,
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pin_none = PINMUX_PULL_NONE | PINMUX_INPUT_ENABLE;
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// MMC3 (sdcard reader)
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pinmux_set_config(PINMUX_SDMMC3_CLK_INDEX,
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PINMUX_SDMMC3_CLK_FUNC_SDMMC3 | pin_none);
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pinmux_set_config(PINMUX_SDMMC3_CMD_INDEX,
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PINMUX_SDMMC3_CMD_FUNC_SDMMC3 | pin_up);
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pinmux_set_config(PINMUX_SDMMC3_DAT0_INDEX,
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PINMUX_SDMMC3_DAT0_FUNC_SDMMC3 | pin_up);
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pinmux_set_config(PINMUX_SDMMC3_DAT1_INDEX,
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PINMUX_SDMMC3_DAT1_FUNC_SDMMC3 | pin_up);
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pinmux_set_config(PINMUX_SDMMC3_DAT2_INDEX,
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PINMUX_SDMMC3_DAT2_FUNC_SDMMC3 | pin_up);
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pinmux_set_config(PINMUX_SDMMC3_DAT3_INDEX,
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PINMUX_SDMMC3_DAT3_FUNC_SDMMC3 | pin_up);
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pinmux_set_config(PINMUX_SDMMC3_CLK_LB_IN_INDEX,
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PINMUX_SDMMC3_CLK_LB_IN_FUNC_SDMMC3 | pin_up);
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pinmux_set_config(PINMUX_SDMMC3_CLK_LB_OUT_INDEX,
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PINMUX_SDMMC3_CLK_LB_OUT_FUNC_SDMMC3 | pin_down);
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// MMC3 Card Detect pin.
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gpio_input_pullup(GPIO(V2));
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// Disable SD card reader power so it can be reset even on warm boot.
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// Payloads must enable power before accessing SD card slots.
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gpio_output(GPIO(R0), 0);
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// MMC4 (eMMC)
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pinmux_set_config(PINMUX_SDMMC4_CLK_INDEX,
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PINMUX_SDMMC4_CLK_FUNC_SDMMC4 | pin_none);
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pinmux_set_config(PINMUX_SDMMC4_CMD_INDEX,
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PINMUX_SDMMC4_CMD_FUNC_SDMMC4 | pin_up);
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pinmux_set_config(PINMUX_SDMMC4_DAT0_INDEX,
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PINMUX_SDMMC4_DAT0_FUNC_SDMMC4 | pin_up);
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pinmux_set_config(PINMUX_SDMMC4_DAT1_INDEX,
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PINMUX_SDMMC4_DAT1_FUNC_SDMMC4 | pin_up);
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pinmux_set_config(PINMUX_SDMMC4_DAT2_INDEX,
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PINMUX_SDMMC4_DAT2_FUNC_SDMMC4 | pin_up);
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pinmux_set_config(PINMUX_SDMMC4_DAT3_INDEX,
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PINMUX_SDMMC4_DAT3_FUNC_SDMMC4 | pin_up);
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pinmux_set_config(PINMUX_SDMMC4_DAT4_INDEX,
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PINMUX_SDMMC4_DAT4_FUNC_SDMMC4 | pin_up);
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pinmux_set_config(PINMUX_SDMMC4_DAT5_INDEX,
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PINMUX_SDMMC4_DAT5_FUNC_SDMMC4 | pin_up);
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pinmux_set_config(PINMUX_SDMMC4_DAT6_INDEX,
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PINMUX_SDMMC4_DAT6_FUNC_SDMMC4 | pin_up);
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pinmux_set_config(PINMUX_SDMMC4_DAT7_INDEX,
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PINMUX_SDMMC4_DAT7_FUNC_SDMMC4 | pin_up);
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/* We pull the USB VBUS signals up but keep them as inputs since the
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* voltage source likes to drive them low on overcurrent conditions */
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gpio_input_pullup(GPIO(N4)); /* USB VBUS EN0 */
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gpio_input_pullup(GPIO(N5)); /* USB VBUS EN1 */
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/* Clock output 1 (for external peripheral) */
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pinmux_set_config(PINMUX_DAP_MCLK1_INDEX,
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PINMUX_DAP_MCLK1_FUNC_EXTPERIPH1 | PINMUX_PULL_NONE);
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/* I2S1 */
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pinmux_set_config(PINMUX_DAP2_DIN_INDEX,
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PINMUX_DAP2_DIN_FUNC_I2S1 | PINMUX_INPUT_ENABLE);
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pinmux_set_config(PINMUX_DAP2_DOUT_INDEX,
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PINMUX_DAP2_DOUT_FUNC_I2S1 | PINMUX_INPUT_ENABLE);
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pinmux_set_config(PINMUX_DAP2_FS_INDEX,
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PINMUX_DAP2_FS_FUNC_I2S1 | PINMUX_INPUT_ENABLE);
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pinmux_set_config(PINMUX_DAP2_SCLK_INDEX,
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PINMUX_DAP2_SCLK_FUNC_I2S1 | PINMUX_INPUT_ENABLE);
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/* PWM1 */
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pinmux_set_config(PINMUX_GPIO_PH1_INDEX,
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PINMUX_GPIO_PH1_FUNC_PWM1 | PINMUX_PULL_NONE);
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/* DP HPD */
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pinmux_set_config(PINMUX_DP_HPD_INDEX,
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PINMUX_DP_HPD_FUNC_DP | PINMUX_INPUT_ENABLE);
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}
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static void setup_kernel_info(void)
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{
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// Setup required information for Linux kernel.
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// pmc.odmdata: [18:19]: console type, [15:17]: UART id.
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// TODO(hungte) This should be done by filling BCT values, or derived
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// from CONFIG_CONSOLE_SERIAL_UART[A-E]. Right now we simply copy the
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// value defined in BCT.
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struct tegra_pmc_regs *pmc = (void*)TEGRA_PMC_BASE;
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writel(0x80080000, &pmc->odmdata);
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// Not strictly info, but kernel graphics driver needs this region locked down
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struct tegra_mc_regs *mc = (void *)TEGRA_MC_BASE;
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writel(0, &mc->video_protect_bom);
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writel(0, &mc->video_protect_size_mb);
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writel(1, &mc->video_protect_reg_ctrl);
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}
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static void setup_ec_spi(void)
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{
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tegra_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS);
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}
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static void mainboard_init(device_t dev)
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{
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set_clock_sources();
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clock_external_output(1); /* For external MAX98090 audio codec. */
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/*
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* Confirmed by NVIDIA hardware team, we need to take ALL audio devices
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* conntected to AHUB (AUDIO, APBIF, I2S, DAM, AMX, ADX, SPDIF, AFC) out
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* of reset and clock-enabled, otherwise reading AHUB devices (In our
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* case, I2S/APBIF/AUDIO<XBAR>) will hang.
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*
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* Note that CLK_H_MEM (MC) and CLK_H_EMC should be already either
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* initialized by BootROM, or in romstage SDRAM initialization.
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*/
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clock_enable_clear_reset(CLK_L_GPIO | CLK_L_I2C1 | CLK_L_SDMMC4 |
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CLK_L_I2S0 | CLK_L_I2S1 | CLK_L_I2S2 |
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CLK_L_SPDIF | CLK_L_USBD | CLK_L_DISP1 |
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CLK_L_HOST1X | CLK_L_PWM,
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CLK_H_I2C2 | CLK_H_PMC | CLK_H_USB3,
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CLK_U_CSITE | CLK_U_SDMMC3,
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CLK_V_I2C4 | CLK_V_EXTPERIPH1 | CLK_V_APBIF |
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CLK_V_AUDIO | CLK_V_I2S3 | CLK_V_I2S4 |
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CLK_V_DAM0 | CLK_V_DAM1 | CLK_V_DAM2,
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CLK_W_DVFS | CLK_W_AMX0 | CLK_W_ADX0,
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CLK_X_DPAUX | CLK_X_SOR0 | CLK_X_AMX1 |
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CLK_X_ADX1 | CLK_X_AFC0 | CLK_X_AFC1 |
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CLK_X_AFC2 | CLK_X_AFC3 | CLK_X_AFC4 |
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CLK_X_AFC5);
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usb_setup_utmip1();
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/* USB2 is the camera, we don't need it in firmware */
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usb_setup_utmip3();
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setup_pinmux();
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i2c_init(0);
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i2c_init(1);
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i2c_init(3);
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setup_kernel_info();
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clock_init_arm_generic_timer();
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setup_ec_spi();
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#if CONFIG_ELOG
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elog_init();
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#endif
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}
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static void mainboard_enable(device_t dev)
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{
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dev->ops->init = &mainboard_init;
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}
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struct chip_operations mainboard_ops = {
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.name = "nyan",
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.enable_dev = mainboard_enable,
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};
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void lb_board(struct lb_header *header)
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{
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struct lb_range *dma;
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dma = (struct lb_range *)lb_new_record(header);
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dma->tag = LB_TAB_DMA;
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dma->size = sizeof(*dma);
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dma->range_start = CONFIG_DRAM_DMA_START;
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dma->range_size = CONFIG_DRAM_DMA_SIZE;
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}
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