mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
6768f39a4b
- CONFIG_CBFS - anything that's conditional on CONFIG_CBFS == 0 - files that were only included for CONFIG_CBFS == 0 In particular: - elfboot - stream boot code - mini-filo and filesystems (depends on stream boot code) After this commit, there is no way to build an image that is not using CBFS anymore. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Myles Watson <mylesgw@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4712 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
208 lines
5.2 KiB
Text
208 lines
5.2 KiB
Text
##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2008 LiPPERT Embedded Computers GmbH
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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## Based on Options.lb from AMD's DB800 mainboard.
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uses CONFIG_HAVE_MP_TABLE
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uses CONFIG_HAVE_PIRQ_TABLE
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uses CONFIG_USE_FALLBACK_IMAGE
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uses CONFIG_HAVE_FALLBACK_BOOT
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uses CONFIG_HAVE_HARD_RESET
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uses CONFIG_HAVE_OPTION_TABLE
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uses CONFIG_USE_OPTION_TABLE
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uses CONFIG_ROM_PAYLOAD
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uses CONFIG_IRQ_SLOT_COUNT
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uses CONFIG_MAINBOARD
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uses CONFIG_MAINBOARD_VENDOR
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uses CONFIG_MAINBOARD_PART_NUMBER
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uses COREBOOT_EXTRA_VERSION
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uses CONFIG_ARCH
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uses CONFIG_FALLBACK_SIZE
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uses CONFIG_STACK_SIZE
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uses CONFIG_HEAP_SIZE
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uses CONFIG_ROM_SIZE
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uses CONFIG_ROM_SECTION_SIZE
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uses CONFIG_ROM_IMAGE_SIZE
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uses CONFIG_ROM_SECTION_SIZE
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uses CONFIG_ROM_SECTION_OFFSET
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uses CONFIG_ROM_PAYLOAD_START
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uses CONFIG_COMPRESS
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uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
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uses CONFIG_COMPRESSED_PAYLOAD_LZMA
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uses CONFIG_PRECOMPRESSED_PAYLOAD
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uses CONFIG_PAYLOAD_SIZE
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uses CONFIG_ROMBASE
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uses CONFIG_RAMBASE
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uses CONFIG_XIP_ROM_SIZE
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uses CONFIG_XIP_ROM_BASE
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uses CONFIG_HAVE_MP_TABLE
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uses CONFIG_CROSS_COMPILE
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uses CC
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uses HOSTCC
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uses CONFIG_OBJCOPY
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uses CONFIG_DEBUG
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uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
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uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
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uses CONFIG_CONSOLE_SERIAL8250
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uses CONFIG_TTYS0_BAUD
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uses CONFIG_TTYS0_BASE
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uses CONFIG_TTYS0_LCS
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uses CONFIG_UDELAY_TSC
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uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
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uses CONFIG_CONSOLE_VGA
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uses CONFIG_PCI_ROM_RUN
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uses CONFIG_VIDEO_MB
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uses CONFIG_USE_DCACHE_RAM
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uses CONFIG_DCACHE_RAM_BASE
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uses CONFIG_DCACHE_RAM_SIZE
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uses CONFIG_USE_PRINTK_IN_CAR
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uses CONFIG_PIRQ_ROUTE
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## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
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default CONFIG_ROM_SIZE = 512 * 1024
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###
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### Build options
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###
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default CONFIG_CONSOLE_VGA = 0
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default CONFIG_VIDEO_MB = 8
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default CONFIG_PCI_ROM_RUN = 0
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##
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## Build code for the fallback boot
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##
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default CONFIG_HAVE_FALLBACK_BOOT = 1
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##
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## no MP table
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##
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default CONFIG_HAVE_MP_TABLE = 0
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##
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## Build code to reset the motherboard from coreboot
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##
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default CONFIG_HAVE_HARD_RESET = 0
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## Delay timer options
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##
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default CONFIG_UDELAY_TSC = 1
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default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
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##
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## Build code to export a programmable irq routing table
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##
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default CONFIG_HAVE_PIRQ_TABLE = 1
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default CONFIG_IRQ_SLOT_COUNT = 7
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default CONFIG_PIRQ_ROUTE = 1
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##
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## Build code to export a CMOS option table
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##
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default CONFIG_HAVE_OPTION_TABLE = 0
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###
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### coreboot layout values
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###
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## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
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default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
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default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
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##
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## enable CACHE_AS_RAM specifics
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##
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default CONFIG_USE_DCACHE_RAM = 1
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default CONFIG_DCACHE_RAM_BASE = 0xc8000
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default CONFIG_DCACHE_RAM_SIZE = 0x08000
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default CONFIG_USE_PRINTK_IN_CAR=1
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##
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## Use a small 8K stack
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##
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default CONFIG_STACK_SIZE = 8 * 1024
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##
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## Use a small 16K heap
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##
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default CONFIG_HEAP_SIZE = 16 * 1024
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##
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## Only use the option table in a normal image
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##
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#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
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default CONFIG_USE_OPTION_TABLE = 0
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default CONFIG_RAMBASE = 0x00004000
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default CONFIG_ROM_PAYLOAD = 1
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##
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## The default compiler
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##
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default CONFIG_CROSS_COMPILE = ""
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default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
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default HOSTCC = "gcc"
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##
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## The Serial Console
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##
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# To Enable the Serial Console
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default CONFIG_CONSOLE_SERIAL8250 = 1
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## Select the serial console baud rate
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default CONFIG_TTYS0_BAUD = 115200
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#default CONFIG_TTYS0_BAUD = 57600
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#default CONFIG_TTYS0_BAUD = 38400
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#default CONFIG_TTYS0_BAUD = 19200
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#default CONFIG_TTYS0_BAUD = 9600
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#default CONFIG_TTYS0_BAUD = 4800
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#default CONFIG_TTYS0_BAUD = 2400
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#default CONFIG_TTYS0_BAUD = 1200
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# Select the serial console base port
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default CONFIG_TTYS0_BASE = 0x3f8
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# Select the serial protocol
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# This defaults to 8 data bits, 1 stop bit, and no parity
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default CONFIG_TTYS0_LCS = 0x3
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# Compile extra debugging code
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default CONFIG_DEBUG = 1
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##
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### Select the coreboot loglevel
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##
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## EMERG 1 system is unusable
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## ALERT 2 action must be taken immediately
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## CRIT 3 critical conditions
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## ERR 4 error conditions
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## WARNING 5 warning conditions
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## NOTICE 6 normal but significant condition
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## INFO 7 informational
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## CONFIG_DEBUG 8 debug-level messages
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## SPEW 9 Way too many details
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## Request this level of debugging output
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default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 8
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## At a maximum only compile in this level of debugging
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default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 8
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end
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