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66e0c4c8c4
CPU_MICROCODE_IN_CBFS was designed to mean that loading microcode updates from a CBFS file is supported, however, the name implies that microcode is present in CBFS. This has recently caused confusion both with contributions from Google, as well as SAGE. Rename this option to SUPPORT_CPU_UCODE_IN_CBFS in order to make it clearer that what is meant is "hey, the code we have for this CPU supports loading microcode updates from CBFS", and prevent further confusion. Change-Id: I394555f690b5ab4cac6fbd3ddbcb740ab1138339 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4482 Reviewed-by: Marc Jones <marc.jones@se-eng.com> Tested-by: build bot (Jenkins)
65 lines
1.3 KiB
Text
65 lines
1.3 KiB
Text
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config CPU_INTEL_HASWELL
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bool
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if CPU_INTEL_HASWELL
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config CPU_SPECIFIC_OPTIONS
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def_bool y
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select SMP
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select SSE2
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select UDELAY_TSC
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select TSC_CONSTANT_RATE
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select SMM_TSEG
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select SMM_MODULES
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select RELOCATABLE_MODULES
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select DYNAMIC_CBMEM
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select SUPPORT_CPU_UCODE_IN_CBFS
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#select AP_IN_SIPI_WAIT
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select TSC_SYNC_MFENCE
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select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
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config BOOTBLOCK_CPU_INIT
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string
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default "cpu/intel/haswell/bootblock.c"
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config SERIAL_CPU_INIT
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bool
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default n
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config SMM_TSEG_SIZE
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hex
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default 0x800000
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config IED_REGION_SIZE
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hex
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default 0x400000
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config SMM_RESERVED_SIZE
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hex
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default 0x100000
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config MICROCODE_INCLUDE_PATH
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string
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default "src/cpu/intel/haswell"
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config RESET_ON_INVALID_RAMSTAGE_CACHE
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bool "Reset the system on S3 wake when ramstage cache invalid."
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default n
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depends on RELOCATABLE_RAMSTAGE
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help
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The haswell romstage code caches the loaded ramstage program
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in SMM space. On S3 wake the romstage will copy over a fresh
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ramstage that was cached in the SMM space. This option determines
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the action to take when the ramstage cache is invalid. If selected
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the system will reset otherwise the ramstage will be reloaded from
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cbfs.
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config MONOTONIC_TIMER_MSR
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def_bool n
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depends on INTEL_LYNXPOINT_LP
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select HAVE_MONOTONIC_TIMER
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help
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Provide a monotonic timer using the 24MHz MSR counter.
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endif
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