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https://github.com/fail0verflow/switch-coreboot.git
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63896e75b4
A video option rom must be added for UMA graphics support. It can be extracted from the supplied UEFI BIOS. ASRock E350M1 support is based on the AMD persimmon project. The major differences are SIO model and DIMM SDP addressing. With this coreboot and seabios, the board can boot DOS from a SATA drive and can boot WinPE from a USB flash drive. I was unable to get Windows setup to run. The board has a socketed SPI flash BIOS chip and a serial port header. The SIO is Nuvoton NCT5572D. Using coreboot's existing Winbond w83627hf is a good enough match to get the serial port and keyboard working. Signed-off-by: Scott Duplichan <scott@notabs.org> Acked-by: Peter Stuge <peter@stuge.se> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6382 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
115 lines
3.3 KiB
C
115 lines
3.3 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <arch/io.h>
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#include <boot/tables.h>
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#include <cpu/x86/msr.h>
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#include <cpu/amd/mtrr.h>
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#include <device/pci_def.h>
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//#include <southbridge/amd/sb800/sb800.h>
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#include "chip.h"
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//#define SMBUS_IO_BASE 0x6000
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/**
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* TODO
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* SB CIMx callback
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*/
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void set_pcie_reset(void)
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{
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}
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/**
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* TODO
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* mainboard specific SB CIMx callback
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*/
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void set_pcie_dereset(void)
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{
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}
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uint64_t uma_memory_base, uma_memory_size;
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/*************************************************
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* enable the dedicated function in e350m1 board.
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*************************************************/
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static void e350m1_enable(device_t dev)
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{
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printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
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#if (CONFIG_GFXUMA == 1)
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msr_t msr, msr2;
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uint32_t sys_mem;
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/* TOP_MEM: the top of DRAM below 4G */
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msr = rdmsr(TOP_MEM);
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printk
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(BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
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__func__, msr.lo, msr.hi);
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/* TOP_MEM2: the top of DRAM above 4G */
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msr2 = rdmsr(TOP_MEM2);
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printk
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(BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n",
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__func__, msr2.lo, msr2.hi);
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/* refer to UMA Size Consideration in Family14h BKDG. */
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sys_mem = msr.lo + 0x1000000; // Ignore 16MB allocated for C6 when finding UMA size, refer MemNGetUmaSizeON()
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if ((msr.hi & 0x0000000F) || (sys_mem >= 0x80000000)) {
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uma_memory_size = 0x18000000; /* >= 2G memory, 384M recommended UMA */
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}
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else {
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if (sys_mem >= 0x40000000) {
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uma_memory_size = 0x10000000; /* >= 1G memory, 256M recommended UMA */
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}
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else {
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uma_memory_size = 0x4000000; /* <1G memory, 64M recommended UMA */
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}
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}
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uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */
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printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n",
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__func__, uma_memory_size, uma_memory_base);
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/* TODO: TOP_MEM2 */
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#else
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uma_memory_size = 0x10000000; /* 256M recommended UMA */
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uma_memory_base = 0x30000000; /* 1GB system memory supported */
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#endif
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}
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int add_mainboard_resources(struct lb_memory *mem)
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{
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/* UMA is removed from system memory in the northbridge code, but
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* in some circumstances we want the memory mentioned as reserved.
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*/
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#if (CONFIG_GFXUMA == 1)
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printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n",
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uma_memory_base, uma_memory_size);
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lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base,
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uma_memory_size);
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#endif
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return 0;
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}
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struct chip_operations mainboard_ops = {
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CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard")
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.enable_dev = e350m1_enable,
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};
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