mirror of
https://github.com/fail0verflow/switch-coreboot.git
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5ec69ed884
This implements the new monotonic timer API using the global multi-core timer (MCT). Change-Id: Id56249ff5d3e0f85808f5754954c83c0bc75f1c1 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/3175 Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins)
116 lines
2.7 KiB
C
116 lines
2.7 KiB
C
/*
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* Copyright 2013 Google Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but without any warranty; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <arch/io.h>
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#include <stdint.h>
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#include <time.h>
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#include "clk.h"
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struct __attribute__((packed)) mct_regs
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{
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uint32_t mct_cfg;
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uint8_t reserved0[0xfc];
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uint32_t g_cnt_l;
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uint32_t g_cnt_u;
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uint8_t reserved1[0x8];
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uint32_t g_cnt_wstat;
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uint8_t reserved2[0xec];
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uint32_t g_comp0_l;
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uint32_t g_comp0_u;
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uint32_t g_comp0_addr_incr;
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uint8_t reserved3[0x4];
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uint32_t g_comp1_l;
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uint32_t g_comp1_u;
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uint32_t g_comp1_addr_incr;
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uint8_t reserved4[0x4];
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uint32_t g_comp2_l;
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uint32_t g_comp2_u;
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uint32_t g_comp2_addr_incr;
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uint8_t reserved5[0x4];
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uint32_t g_comp3_l;
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uint32_t g_comp3_u;
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uint32_t g_comp3_addr_incr;
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uint8_t reserved6[0x4];
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uint32_t g_tcon;
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uint32_t g_int_cstat;
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uint32_t g_int_enb;
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uint32_t g_wstat;
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uint8_t reserved7[0xb0];
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uint32_t l0_tcntb;
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uint32_t l0_tcnto;
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uint32_t l0_icntb;
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uint32_t l0_icnto;
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uint32_t l0_frcntb;
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uint32_t l0_frcnto;
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uint8_t reserved8[0x8];
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uint32_t l0_tcon;
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uint8_t reserved9[0xc];
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uint32_t l0_int_cstat;
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uint32_t l0_int_enb;
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uint8_t reserved10[0x8];
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uint32_t l0_wstat;
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uint8_t reserved11[0xbc];
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uint32_t l1_tcntb;
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uint32_t l1_tcnto;
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uint32_t l1_icntb;
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uint32_t l1_icnto;
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uint32_t l1_frcntb;
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uint32_t l1_frcnto;
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uint8_t reserved12[0x8];
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uint32_t l1_tcon;
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uint8_t reserved13[0xc];
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uint32_t l1_int_cstat;
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uint32_t l1_int_enb;
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uint8_t reserved14[0x8];
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uint32_t l1_wstat;
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};
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static int enabled = 0;
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static struct mct_regs *const mct =
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(struct mct_regs *)MCT_ADDRESS;
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uint64_t mct_raw_value(void)
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{
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if (!enabled) {
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writel(readl(&mct->g_tcon) | (0x1 << 8), &mct->g_tcon);
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enabled = 1;
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}
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uint64_t upper = readl(&mct->g_cnt_u);
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uint64_t lower = readl(&mct->g_cnt_l);
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return (upper << 32) | lower;
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}
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void timer_start(void)
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{
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writel(readl(&mct->g_tcon) | (0x1 << 8), &mct->g_tcon);
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enabled = 1;
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}
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u32 timer_us(void)
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{
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uint64_t raw = mct_raw_value();
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static uint32_t ticks_per_microsecond = MCT_HZ/1000000;
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uint32_t usec = raw / ticks_per_microsecond;
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return usec;
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}
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