mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
5ec69ed884
This implements the new monotonic timer API using the global multi-core timer (MCT). Change-Id: Id56249ff5d3e0f85808f5754954c83c0bc75f1c1 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/3175 Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins)
590 lines
16 KiB
C
590 lines
16 KiB
C
/*
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* (C) Copyright 2012 Samsung Electronics
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* Minkyu Kang <mk7.kang@samsung.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#ifndef __EXYNOS5_CLK_H__
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#define __EXYNOS5_CLK_H__
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#include <cpu/samsung/exynos5-common/clk.h>
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#include <cpu/samsung/exynos5250/pinmux.h>
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#define MCT_ADDRESS 0x101c0000
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#define MCT_HZ 24000000
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/*
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* Set mshci controller instances clock drivder
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*
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* @param enum periph_id instance of the mshci controller
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*
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* Return 0 if ok else -1
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*/
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int clock_set_mshci(enum periph_id peripheral);
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/*
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* Sets the epll clockrate
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*
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* @param rate Required clock rate to the presacaler in Hz
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*
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* Return 0 if ok else -1
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*/
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int clock_epll_set_rate(unsigned long rate);
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/*
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* selects the clk source for I2S MCLK
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*/
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void clock_select_i2s_clk_source(void);
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/*
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* Set prescaler division based on input and output frequency
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* for i2s audio clock
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*
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* @param src_frq Source frequency in Hz
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* @param dst_frq Required MCLK frequency in Hz
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*
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* Return 0 if ok else -1
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*/
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int clock_set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq);
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/* FIXME(dhendrix): below is stuff from arch/arm/include/asm/arch-exynos5/clock.h
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(as opposed to the two clk.h files as they were named in u-boot... */
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struct exynos5_clock {
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unsigned int apll_lock; /* base + 0 */
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unsigned char res1[0xfc];
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unsigned int apll_con0;
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unsigned int apll_con1;
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unsigned char res2[0xf8];
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unsigned int src_cpu;
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unsigned char res3[0x1fc];
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unsigned int mux_stat_cpu;
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unsigned char res4[0xfc];
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unsigned int div_cpu0;
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unsigned int div_cpu1;
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unsigned char res5[0xf8];
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unsigned int div_stat_cpu0;
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unsigned int div_stat_cpu1;
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unsigned char res6[0x1f8];
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unsigned int gate_sclk_cpu;
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unsigned char res7[0x1fc];
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unsigned int clkout_cmu_cpu;
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unsigned int clkout_cmu_cpu_div_stat;
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unsigned char res8[0x5f8];
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unsigned int armclk_stopctrl; /* base + 0x1000 */
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unsigned int atclk_stopctrl;
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unsigned char res9[0x8];
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unsigned int parityfail_status;
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unsigned int parityfail_clear;
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unsigned char res10[0x8];
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unsigned int pwr_ctrl;
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unsigned int pwr_ctr2;
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unsigned char res11[0xd8];
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unsigned int apll_con0_l8;
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unsigned int apll_con0_l7;
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unsigned int apll_con0_l6;
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unsigned int apll_con0_l5;
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unsigned int apll_con0_l4;
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unsigned int apll_con0_l3;
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unsigned int apll_con0_l2;
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unsigned int apll_con0_l1;
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unsigned int iem_control;
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unsigned char res12[0xdc];
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unsigned int apll_con1_l8;
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unsigned int apll_con1_l7;
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unsigned int apll_con1_l6;
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unsigned int apll_con1_l5;
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unsigned int apll_con1_l4;
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unsigned int apll_con1_l3;
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unsigned int apll_con1_l2;
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unsigned int apll_con1_l1;
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unsigned char res13[0xe0];
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unsigned int div_iem_l8;
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unsigned int div_iem_l7;
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unsigned int div_iem_l6;
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unsigned int div_iem_l5;
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unsigned int div_iem_l4;
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unsigned int div_iem_l3;
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unsigned int div_iem_l2;
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unsigned int div_iem_l1;
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unsigned char res14[0x2ce0];
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unsigned int mpll_lock; /* base + 0x4000 */
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unsigned char res15[0xfc];
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unsigned int mpll_con0;
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unsigned int mpll_con1;
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unsigned char res16[0xf8];
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unsigned int src_core0;
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unsigned int src_core1;
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unsigned char res17[0xf8];
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unsigned int src_mask_core;
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unsigned char res18[0x100];
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unsigned int mux_stat_core1;
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unsigned char res19[0xf8];
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unsigned int div_core0;
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unsigned int div_core1;
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unsigned int div_sysrgt;
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unsigned char res20[0xf4];
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unsigned int div_stat_core0;
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unsigned int div_stat_core1;
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unsigned int div_stat_sysrgt;
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unsigned char res21[0x2f4];
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unsigned int gate_ip_core;
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unsigned int gate_ip_sysrgt;
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unsigned char res22[0xf8];
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unsigned int clkout_cmu_core;
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unsigned int clkout_cmu_core_div_stat;
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unsigned char res23[0x5f8];
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unsigned int dcgidx_map0; /* base + 0x5000 */
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unsigned int dcgidx_map1;
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unsigned int dcgidx_map2;
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unsigned char res24[0x14];
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unsigned int dcgperf_map0;
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unsigned int dcgperf_map1;
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unsigned char res25[0x18];
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unsigned int dvcidx_map;
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unsigned char res26[0x1c];
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unsigned int freq_cpu;
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unsigned int freq_dpm;
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unsigned char res27[0x18];
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unsigned int dvsemclk_en;
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unsigned int maxperf;
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unsigned char res28[0x3478];
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unsigned int div_acp; /* base + 0x8500 */
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unsigned char res29[0xfc];
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unsigned int div_stat_acp;
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unsigned char res30[0x1fc];
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unsigned int gate_ip_acp;
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unsigned char res31a[0xfc];
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unsigned int div_syslft;
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unsigned char res31b[0xc];
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unsigned int div_stat_syslft;
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unsigned char res31c[0xc];
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unsigned int gate_bus_syslft;
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unsigned char res31d[0xdc];
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unsigned int clkout_cmu_acp;
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unsigned int clkout_cmu_acp_div_stat;
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unsigned char res32[0x38f8];
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unsigned int div_isp0; /* base + 0xc300 */
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unsigned int div_isp1;
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unsigned int div_isp2;
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unsigned char res33[0xf4];
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unsigned int div_stat_isp0; /* base + 0xc400 */
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unsigned int div_stat_isp1;
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unsigned int div_stat_isp2;
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unsigned char res34[0x3f4];
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unsigned int gate_ip_isp0; /* base + 0xc800 */
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unsigned int gate_ip_isp1;
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unsigned char res35[0xf8];
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unsigned int gate_sclk_isp;
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unsigned char res36[0xc];
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unsigned int mcuisp_pwr_ctrl;
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unsigned char res37[0xec];
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unsigned int clkout_cmu_isp;
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unsigned int clkout_cmu_isp_div_stat;
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unsigned char res38[0x3618];
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unsigned int cpll_lock; /* base + 0x10020 */
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unsigned char res39[0xc];
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unsigned int epll_lock;
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unsigned char res40[0xc];
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unsigned int vpll_lock;
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unsigned char res41a[0xc];
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unsigned int gpll_lock;
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unsigned char res41b[0xcc];
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unsigned int cpll_con0;
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unsigned int cpll_con1;
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unsigned char res42[0x8];
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unsigned int epll_con0;
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unsigned int epll_con1;
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unsigned int epll_con2;
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unsigned char res43[0x4];
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unsigned int vpll_con0;
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unsigned int vpll_con1;
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unsigned int vpll_con2;
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unsigned char res44a[0x4];
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unsigned int gpll_con0;
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unsigned int gpll_con1;
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unsigned char res44b[0xb8];
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unsigned int src_top0;
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unsigned int src_top1;
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unsigned int src_top2;
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unsigned int src_top3;
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unsigned int src_gscl;
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unsigned int src_disp0_0;
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unsigned int src_disp0_1;
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unsigned int src_disp1_0;
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unsigned int src_disp1_1;
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unsigned char res46[0xc];
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unsigned int src_mau;
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unsigned int src_fsys;
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unsigned char res47[0x8];
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unsigned int src_peric0;
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unsigned int src_peric1;
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unsigned char res48[0x18];
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unsigned int sclk_src_isp;
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unsigned char res49[0x9c];
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unsigned int src_mask_top;
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unsigned char res50[0xc];
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unsigned int src_mask_gscl;
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unsigned int src_mask_disp0_0;
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unsigned int src_mask_disp0_1;
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unsigned int src_mask_disp1_0;
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unsigned int src_mask_disp1_1;
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unsigned int src_mask_maudio;
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unsigned char res52[0x8];
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unsigned int src_mask_fsys;
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unsigned char res53[0xc];
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unsigned int src_mask_peric0;
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unsigned int src_mask_peric1;
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unsigned char res54[0x18];
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unsigned int src_mask_isp;
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unsigned char res55[0x9c];
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unsigned int mux_stat_top0;
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unsigned int mux_stat_top1;
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unsigned int mux_stat_top2;
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unsigned int mux_stat_top3;
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unsigned char res56[0xf0];
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unsigned int div_top0;
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unsigned int div_top1;
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unsigned char res57[0x8];
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unsigned int div_gscl;
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unsigned int div_disp0_0;
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unsigned int div_disp0_1;
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unsigned int div_disp1_0;
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unsigned int div_disp1_1;
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unsigned char res59[0x8];
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unsigned int div_gen;
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unsigned char res60[0x4];
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unsigned int div_mau;
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unsigned int div_fsys0;
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unsigned int div_fsys1;
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unsigned int div_fsys2;
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unsigned int div_fsys3;
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unsigned int div_peric0;
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unsigned int div_peric1;
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unsigned int div_peric2;
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unsigned int div_peric3;
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unsigned int div_peric4;
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unsigned int div_peric5;
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unsigned char res61[0x10];
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unsigned int sclk_div_isp;
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unsigned char res62[0xc];
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unsigned int div2_ratio0;
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unsigned int div2_ratio1;
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unsigned char res63[0x8];
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unsigned int div4_ratio;
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unsigned char res64[0x6c];
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unsigned int div_stat_top0;
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unsigned int div_stat_top1;
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unsigned char res65[0x8];
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unsigned int div_stat_gscl;
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unsigned int div_stat_disp0_0;
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unsigned int div_stat_disp0_1;
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unsigned int div_stat_disp1_0;
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unsigned int div_stat_disp1_1;
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unsigned char res67[0x8];
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unsigned int div_stat_gen;
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unsigned char res68[0x4];
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unsigned int div_stat_maudio;
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unsigned int div_stat_fsys0;
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unsigned int div_stat_fsys1;
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unsigned int div_stat_fsys2;
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unsigned int div_stat_fsys3;
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unsigned int div_stat_peric0;
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unsigned int div_stat_peric1;
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unsigned int div_stat_peric2;
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unsigned int div_stat_peric3;
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unsigned int div_stat_peric4;
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unsigned int div_stat_peric5;
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unsigned char res69[0x10];
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unsigned int sclk_div_stat_isp;
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unsigned char res70[0xc];
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unsigned int div2_stat0;
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unsigned int div2_stat1;
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unsigned char res71[0x8];
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unsigned int div4_stat;
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unsigned char res72[0x180];
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unsigned int gate_top_sclk_disp0;
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unsigned int gate_top_sclk_disp1;
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unsigned int gate_top_sclk_gen;
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unsigned char res74[0xc];
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unsigned int gate_top_sclk_mau;
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unsigned int gate_top_sclk_fsys;
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unsigned char res75[0xc];
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unsigned int gate_top_sclk_peric;
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unsigned char res76[0x1c];
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unsigned int gate_top_sclk_isp;
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unsigned char res77[0xac];
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unsigned int gate_ip_gscl;
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unsigned int gate_ip_disp0;
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unsigned int gate_ip_disp1;
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unsigned int gate_ip_mfc;
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unsigned int gate_ip_g3d;
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unsigned int gate_ip_gen;
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unsigned char res79[0xc];
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unsigned int gate_ip_fsys;
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unsigned char res80[0x4];
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unsigned int gate_ip_gps;
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unsigned int gate_ip_peric;
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unsigned char res81[0xc];
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unsigned int gate_ip_peris;
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unsigned char res82[0x1c];
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unsigned int gate_block;
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unsigned char res83[0x7c];
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unsigned int clkout_cmu_top;
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unsigned int clkout_cmu_top_div_stat;
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unsigned char res84[0x37f8];
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unsigned int src_lex; /* base + 0x14200 */
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unsigned char res85[0x1fc];
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unsigned int mux_stat_lex;
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unsigned char res85b[0xfc];
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unsigned int div_lex;
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unsigned char res86[0xfc];
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unsigned int div_stat_lex;
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unsigned char res87[0x1fc];
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unsigned int gate_ip_lex;
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unsigned char res88[0x1fc];
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unsigned int clkout_cmu_lex;
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unsigned int clkout_cmu_lex_div_stat;
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unsigned char res89[0x3af8];
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unsigned int div_r0x; /* base + 0x18500 */
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unsigned char res90[0xfc];
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unsigned int div_stat_r0x;
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unsigned char res91[0x1fc];
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unsigned int gate_ip_r0x;
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unsigned char res92[0x1fc];
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unsigned int clkout_cmu_r0x;
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unsigned int clkout_cmu_r0x_div_stat;
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unsigned char res94[0x3af8];
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unsigned int div_r1x; /* base + 0x1c500 */
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unsigned char res95[0xfc];
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unsigned int div_stat_r1x;
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unsigned char res96[0x1fc];
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unsigned int gate_ip_r1x;
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unsigned char res97[0x1fc];
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unsigned int clkout_cmu_r1x;
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unsigned int clkout_cmu_r1x_div_stat;
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unsigned char res98[0x3608];
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unsigned int bpll_lock; /* base + 0x2000c */
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unsigned char res99[0xfc];
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unsigned int bpll_con0;
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unsigned int bpll_con1;
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unsigned char res100[0xe8];
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unsigned int src_cdrex;
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unsigned char res101[0x1fc];
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unsigned int mux_stat_cdrex;
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unsigned char res102[0xfc];
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unsigned int div_cdrex;
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unsigned int div_cdrex2;
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unsigned char res103[0xf8];
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unsigned int div_stat_cdrex;
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unsigned char res104[0x2fc];
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unsigned int gate_ip_cdrex;
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unsigned char res105[0xc];
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unsigned int c2c_monitor;
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unsigned int dmc_pwr_ctrl;
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unsigned char res106[0x4];
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unsigned int drex2_pause;
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unsigned char res107[0xe0];
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unsigned int clkout_cmu_cdrex;
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unsigned int clkout_cmu_cdrex_div_stat;
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unsigned char res108[0x8];
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unsigned int lpddr3phy_ctrl;
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unsigned char res109a[0xc];
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unsigned int lpddr3phy_con3;
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unsigned int pll_div2_sel;
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unsigned char res109b[0xf5e4];
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};
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struct exynos5_mct_regs {
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uint32_t mct_cfg;
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uint8_t reserved0[0xfc];
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uint32_t g_cnt_l;
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uint32_t g_cnt_u;
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uint8_t reserved1[0x8];
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uint32_t g_cnt_wstat;
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uint8_t reserved2[0xec];
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uint32_t g_comp0_l;
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uint32_t g_comp0_u;
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uint32_t g_comp0_addr_incr;
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uint8_t reserved3[0x4];
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uint32_t g_comp1_l;
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uint32_t g_comp1_u;
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uint32_t g_comp1_addr_incr;
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uint8_t reserved4[0x4];
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uint32_t g_comp2_l;
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uint32_t g_comp2_u;
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uint32_t g_comp2_addr_incr;
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uint8_t reserved5[0x4];
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uint32_t g_comp3_l;
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uint32_t g_comp3_u;
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uint32_t g_comp3_addr_incr;
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uint8_t reserved6[0x4];
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uint32_t g_tcon;
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uint32_t g_int_cstat;
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uint32_t g_int_enb;
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uint32_t g_wstat;
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uint8_t reserved7[0xb0];
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uint32_t l0_tcntb;
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uint32_t l0_tcnto;
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uint32_t l0_icntb;
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uint32_t l0_icnto;
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uint32_t l0_frcntb;
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uint32_t l0_frcnto;
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uint8_t reserved8[0x8];
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uint32_t l0_tcon;
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uint8_t reserved9[0xc];
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uint32_t l0_int_cstat;
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uint32_t l0_int_enb;
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uint8_t reserved10[0x8];
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uint32_t l0_wstat;
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uint8_t reserved11[0xbc];
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uint32_t l1_tcntb;
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uint32_t l1_tcnto;
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uint32_t l1_icntb;
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|
uint32_t l1_icnto;
|
|
uint32_t l1_frcntb;
|
|
uint32_t l1_frcnto;
|
|
uint8_t reserved12[0x8];
|
|
uint32_t l1_tcon;
|
|
uint8_t reserved13[0xc];
|
|
uint32_t l1_int_cstat;
|
|
uint32_t l1_int_enb;
|
|
uint8_t reserved14[0x8];
|
|
uint32_t l1_wstat;
|
|
};
|
|
|
|
#define EXYNOS5_EPLLCON0_LOCKED_SHIFT 29 /* EPLL Locked bit position*/
|
|
#define EPLL_SRC_CLOCK 24000000 /*24 MHz Cristal Input */
|
|
#define TIMEOUT_EPLL_LOCK 1000
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|
|
|
#define AUDIO_0_RATIO_MASK 0x0f
|
|
#define AUDIO_1_RATIO_MASK 0x0f
|
|
|
|
#define CLK_SRC_PERIC1 0x254
|
|
#define AUDIO1_SEL_MASK 0xf
|
|
#define CLK_SRC_AUDIOCDCLK1 0x0
|
|
#define CLK_SRC_XXTI 0x1
|
|
#define CLK_SRC_SCLK_EPLL 0x7
|
|
|
|
/* CON0 bit-fields */
|
|
#define EPLL_CON0_MDIV_MASK 0x1ff
|
|
#define EPLL_CON0_PDIV_MASK 0x3f
|
|
#define EPLL_CON0_SDIV_MASK 0x7
|
|
#define EPLL_CON0_LOCKED_SHIFT 29
|
|
#define EPLL_CON0_MDIV_SHIFT 16
|
|
#define EPLL_CON0_PDIV_SHIFT 8
|
|
#define EPLL_CON0_SDIV_SHIFT 0
|
|
#define EPLL_CON0_LOCK_DET_EN_SHIFT 28
|
|
#define EPLL_CON0_LOCK_DET_EN_MASK 1
|
|
|
|
/* structure for epll configuration used in audio clock configuration */
|
|
struct st_epll_con_val {
|
|
unsigned int freq_out; /* frequency out */
|
|
unsigned int en_lock_det; /* enable lock detect */
|
|
unsigned int m_div; /* m divider value */
|
|
unsigned int p_div; /* p divider value */
|
|
unsigned int s_div; /* s divider value */
|
|
unsigned int k_dsm; /* k value of delta signal modulator */
|
|
};
|
|
|
|
/**
|
|
* Low-level function to set the clock pre-ratio for a peripheral
|
|
*
|
|
* @param periph_id Peripheral ID of peripheral to change
|
|
* @param divisor New divisor for this peripheral's clock
|
|
*/
|
|
void clock_ll_set_pre_ratio(enum periph_id periph_id, unsigned divisor);
|
|
|
|
/**
|
|
* Low-level function to set the clock ratio for a peripheral
|
|
*
|
|
* @param periph_id Peripheral ID of peripheral to change
|
|
* @param divisor New divisor for this peripheral's clock
|
|
*/
|
|
void clock_ll_set_ratio(enum periph_id periph_id, unsigned divisor);
|
|
|
|
/**
|
|
* Low-level function that selects the best clock scalars for a given rate and
|
|
* sets up the given peripheral's clock accordingly.
|
|
*
|
|
* @param periph_id Peripheral ID of peripheral to change
|
|
* @param rate Desired clock rate in Hz
|
|
*
|
|
* @return zero on success, negative on error
|
|
*/
|
|
int clock_set_rate(enum periph_id periph_id, unsigned int rate);
|
|
|
|
/**
|
|
* Decode a peripheral ID from a device node.
|
|
*
|
|
* Drivers should always use this function since the actual means of
|
|
* encoding this information may change in the future as fdt support for
|
|
* exynos evolves.
|
|
*
|
|
* @param blob FDT blob to read from
|
|
* @param node Node containing the information
|
|
*/
|
|
int clock_decode_periph_id(const void *blob, int node);
|
|
|
|
/* Clock gate unused IP */
|
|
void clock_gate(void);
|
|
|
|
enum ddr_mode;
|
|
enum mem_manuf;
|
|
|
|
const char *clock_get_mem_type_name(enum ddr_mode mem_type);
|
|
|
|
const char *clock_get_mem_manuf_name(enum mem_manuf mem_manuf);
|
|
|
|
/*
|
|
* TODO(sjg@chromium.org): Remove this when we have more SPL space.
|
|
* At present we are using 14148 of 14336 bytes. If we change this function
|
|
* to be exported in SPL, we go over the edge.
|
|
*/
|
|
/**
|
|
* Get the required memory type and speed (Main U-Boot version).
|
|
*
|
|
* This should use the device tree. For now we cannot since this function is
|
|
* called before the FDT is available.
|
|
*
|
|
* @param mem_type Returns memory type
|
|
* @param frequency_mhz Returns memory speed in MHz
|
|
* @param arm_freq Returns ARM clock speed in MHz
|
|
* @param mem_manuf Return Memory Manufacturer name
|
|
* @return 0 if all ok (if not, this function currently does not return)
|
|
*/
|
|
int clock_get_mem_selection(enum ddr_mode *mem_type,
|
|
unsigned *frequency_mhz, unsigned *arm_freq,
|
|
enum mem_manuf *mem_manuf);
|
|
|
|
uint64_t mct_raw_value(void);
|
|
|
|
#endif
|