mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
5e4770fc02
Fix the bus location for Qemu IDE. This patch only provides the needed infrastructure for per-device subsystem IDs, it does not hook them up to the PCI core yet, so this patch is a no-op. By the way, the on_mainboard property is activating lots of completely untested code paths in v3, so someone might want to audit them. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://coreboot.org/repository/coreboot-v3@844 f3766cd6-281f-0410-b1cd-43a5c92072e9
41 lines
1.3 KiB
Text
41 lines
1.3 KiB
Text
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007 Ronald G. Minnich <rminnich@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/{
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mainboard_vendor = "Emulation";
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mainboard_name = "QEMU x86";
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mainboard_pci_subsystem_vendor = "0x15ad";
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mainboard_pci_subsystem_device = "0x1976";
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device_operations = "qemuvga_pci_ops_dev";
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cpus {};
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domain@0 {
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/config/("northbridge/intel/i440bxemulation/domain");
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bus@0 {
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pci@0,0 {
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};
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pci@1,1 {
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/config/("southbridge/intel/i82371eb/ide");
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subsystem_vendor = "0x15ad";
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subsystem_device = "0x1976";
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on_mainboard;
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};
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};
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};
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};
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