mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
dd8367006c
This makes the CAR implementations a lot more readable, shorter and easier to follow, and also reduces the amount of uselessly duplicated code. For example there are more than 12 open-coded "enable cache" instances spread all over the place (and 12 "disable cache" ones), multiple "enable mtrr", "save BIST", "restore BIST", etc. etc. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5902 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
75 lines
1.8 KiB
C
75 lines
1.8 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com>
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* Copyright (C) 2007-2008 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <cpu/x86/mtrr.h>
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/* Save the BIST result. */
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#define save_bist_result() \
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movl %eax, %ebp
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/* Restore the BIST result. */
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#define restore_bist_result() \
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movl %ebp, %eax
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/* Enable cache. */
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#define enable_cache() \
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movl %cr0, %eax; \
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andl $(~((1 << 30) | (1 << 29))), %eax; \
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movl %eax, %cr0
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/* Disable cache. */
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#define disable_cache() \
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movl %cr0, %eax; \
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orl $(1 << 30), %eax; \
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movl %eax, %cr0
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/* Enable MTRR. */
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#define enable_mtrr() \
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movl $MTRRdefType_MSR, %ecx; \
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rdmsr; \
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orl $(1 << 11), %eax; \
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wrmsr
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/* Disable MTRR. */
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#define disable_mtrr() \
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movl $MTRRdefType_MSR, %ecx; \
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rdmsr; \
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andl $(~(1 << 11)), %eax; \
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wrmsr
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/* Enable L2 cache. */
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#define enable_l2_cache() \
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movl $0x11e, %ecx; \
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rdmsr; \
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orl $(1 << 8), %eax; \
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wrmsr
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/* Enable SSE. */
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#define enable_sse() \
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movl %cr4, %eax; \
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orl $(3 << 9), %eax; \
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movl %eax, %cr4
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/* Disable SSE. */
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#define disable_sse() \
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movl %cr4, %eax; \
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andl $~(3 << 9), %eax; \
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movl %eax, %cr4
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