mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
58bf6ac2ab
This is more consistent with newer Intel targets. This a static struct so it is initialized to 0 by default. To make it more readable: * only setting to GPIO mode is made explicit; * only pins in GPIO mode are either set to input or output since this is ignored in native mode; * only output pins are set high or low, since this is read-only on input; * blink is only operational on output pins, non-blink is not set explicitly; * invert is only operational on input pins, non-invert is not set explicitly. Change-Id: I05f9c52dee78b7120b225982c040e3dcc8ee3e4e Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Original-Reviewed-on: https://review.coreboot.org/17639 Original-Tested-by: build bot (Jenkins) Original-Reviewed-by: Nico Huber <nico.h@gmx.de> Original-Reviewed-by: Patrick Rudolph <siro@das-labor.org> Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/425981 Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
116 lines
2.9 KiB
C
116 lines
2.9 KiB
C
#include <southbridge/intel/common/gpio.h>
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static const struct pch_gpio_set1 pch_gpio_set1_mode = {
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.gpio6 = GPIO_MODE_GPIO,
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.gpio7 = GPIO_MODE_GPIO,
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.gpio8 = GPIO_MODE_GPIO,
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.gpio9 = GPIO_MODE_GPIO,
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.gpio10 = GPIO_MODE_GPIO,
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.gpio12 = GPIO_MODE_GPIO,
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.gpio13 = GPIO_MODE_GPIO,
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.gpio14 = GPIO_MODE_GPIO,
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.gpio15 = GPIO_MODE_GPIO,
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.gpio16 = GPIO_MODE_GPIO,
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.gpio17 = GPIO_MODE_GPIO,
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.gpio18 = GPIO_MODE_GPIO,
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.gpio19 = GPIO_MODE_GPIO,
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.gpio20 = GPIO_MODE_GPIO,
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.gpio24 = GPIO_MODE_GPIO,
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.gpio25 = GPIO_MODE_GPIO,
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.gpio26 = GPIO_MODE_GPIO,
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.gpio27 = GPIO_MODE_GPIO,
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.gpio28 = GPIO_MODE_GPIO,
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};
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static const struct pch_gpio_set1 pch_gpio_set1_direction = {
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.gpio6 = GPIO_DIR_INPUT,
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.gpio7 = GPIO_DIR_INPUT,
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.gpio8 = GPIO_DIR_INPUT,
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.gpio9 = GPIO_DIR_INPUT,
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.gpio10 = GPIO_DIR_INPUT,
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.gpio12 = GPIO_DIR_OUTPUT,
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.gpio13 = GPIO_DIR_INPUT,
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.gpio14 = GPIO_DIR_INPUT,
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.gpio15 = GPIO_DIR_INPUT,
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.gpio16 = GPIO_DIR_OUTPUT,
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.gpio17 = GPIO_DIR_OUTPUT,
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.gpio18 = GPIO_DIR_OUTPUT,
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.gpio19 = GPIO_DIR_INPUT,
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.gpio20 = GPIO_DIR_OUTPUT,
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.gpio24 = GPIO_DIR_OUTPUT,
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.gpio25 = GPIO_DIR_OUTPUT,
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.gpio26 = GPIO_DIR_OUTPUT,
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.gpio27 = GPIO_DIR_OUTPUT,
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.gpio28 = GPIO_DIR_OUTPUT,
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};
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static const struct pch_gpio_set1 pch_gpio_set1_level = {
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.gpio12 = GPIO_LEVEL_LOW,
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.gpio16 = GPIO_LEVEL_HIGH,
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.gpio17 = GPIO_LEVEL_HIGH,
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.gpio18 = GPIO_LEVEL_HIGH,
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.gpio20 = GPIO_LEVEL_HIGH,
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.gpio24 = GPIO_LEVEL_HIGH,
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.gpio25 = GPIO_LEVEL_HIGH,
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.gpio26 = GPIO_LEVEL_LOW,
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.gpio27 = GPIO_LEVEL_HIGH,
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.gpio28 = GPIO_LEVEL_LOW,
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};
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static const struct pch_gpio_set1 pch_gpio_set1_invert = {
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.gpio7 = GPIO_INVERT,
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.gpio8 = GPIO_INVERT,
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.gpio13 = GPIO_INVERT,
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};
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static const struct pch_gpio_set1 pch_gpio_set1_blink = {
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};
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static const struct pch_gpio_set2 pch_gpio_set2_mode = {
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.gpio32 = GPIO_MODE_GPIO,
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.gpio33 = GPIO_MODE_GPIO,
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.gpio34 = GPIO_MODE_GPIO,
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.gpio35 = GPIO_MODE_GPIO,
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.gpio36 = GPIO_MODE_GPIO,
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.gpio37 = GPIO_MODE_GPIO,
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.gpio38 = GPIO_MODE_GPIO,
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.gpio39 = GPIO_MODE_GPIO,
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.gpio48 = GPIO_MODE_GPIO,
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};
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static const struct pch_gpio_set2 pch_gpio_set2_direction = {
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.gpio32 = GPIO_DIR_OUTPUT,
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.gpio33 = GPIO_DIR_OUTPUT,
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.gpio34 = GPIO_DIR_OUTPUT,
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.gpio35 = GPIO_DIR_OUTPUT,
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.gpio36 = GPIO_DIR_INPUT,
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.gpio37 = GPIO_DIR_INPUT,
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.gpio38 = GPIO_DIR_OUTPUT,
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.gpio39 = GPIO_DIR_OUTPUT,
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.gpio48 = GPIO_DIR_OUTPUT,
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};
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static const struct pch_gpio_set2 pch_gpio_set2_level = {
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.gpio32 = GPIO_LEVEL_HIGH,
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.gpio33 = GPIO_LEVEL_LOW,
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.gpio34 = GPIO_LEVEL_HIGH,
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.gpio35 = GPIO_LEVEL_LOW,
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.gpio38 = GPIO_LEVEL_LOW,
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.gpio39 = GPIO_LEVEL_LOW,
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.gpio48 = GPIO_LEVEL_HIGH,
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};
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const struct pch_gpio_map mainboard_gpio_map = {
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.set1 = {
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.mode = &pch_gpio_set1_mode,
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.direction = &pch_gpio_set1_direction,
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.level = &pch_gpio_set1_level,
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.blink = &pch_gpio_set1_blink,
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.invert = &pch_gpio_set1_invert,
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},
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.set2 = {
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.mode = &pch_gpio_set2_mode,
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.direction = &pch_gpio_set2_direction,
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.level = &pch_gpio_set2_level,
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},
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};
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