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board. This is done via the ec_init routine in a source file in the mainboard/gigabyte/m57sli directory. A Config variable 'HAVE_FANCTL' has been added to notify superio.c to get the ec_init externally. I (Ward) have tested this on the PLCC and the SOIC/SPI version of this board. It works. Signed-off-by: Ronald Hoogenboom <hoogenboom30@zonnet.nl> Acked-by: Ward Vandewege <ward@gnu.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3116 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
174 lines
4.8 KiB
C
174 lines
4.8 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
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* Copyright (C) 2007 AMD
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* (Written by Yinghai Lu <yinghai.lu@amd.com> for AMD)
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* Copyright (C) 2007 Ward Vandewege <ward@gnu.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <device/device.h>
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#include <device/pnp.h>
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#include <console/console.h>
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#include <uart8250.h>
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#include <pc80/keyboard.h>
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#include <arch/io.h>
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#include "chip.h"
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#include "it8716f.h"
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/* Base address 0x2e: 0x87 0x01 0x55 0x55. */
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/* Base address 0x4e: 0x87 0x01 0x55 0xaa. */
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static void pnp_enter_ext_func_mode(device_t dev)
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{
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outb(0x87, dev->path.u.pnp.port);
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outb(0x01, dev->path.u.pnp.port);
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outb(0x55, dev->path.u.pnp.port);
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if (dev->path.u.pnp.port == 0x4e) {
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outb(0xaa, dev->path.u.pnp.port);
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} else {
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outb(0x55, dev->path.u.pnp.port);
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}
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}
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static void pnp_exit_ext_func_mode(device_t dev)
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{
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pnp_write_config(dev, 0x02, 0x02);
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}
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static void pnp_write_index(uint16_t port_base, uint8_t reg, uint8_t value)
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{
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outb(reg, port_base);
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outb(value, port_base + 1);
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}
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static uint8_t pnp_read_index(uint16_t port_base, uint8_t reg)
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{
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outb(reg, port_base);
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return inb(port_base + 1);
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}
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#ifdef HAVE_FANCTL
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extern void init_ec(uint16_t base);
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#else
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static void init_ec(uint16_t base)
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{
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uint8_t value;
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/* Read out current value of FAN_CTL control register (0x14). */
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value = pnp_read_index(base, 0x14);
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printk_debug("FAN_CTL: reg = 0x%04x, read value = 0x%02x\r\n",
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base + 0x14, value);
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/* Set FAN_CTL control register (0x14) polarity to high, and
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activate fans 1, 2 and 3. */
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pnp_write_index(base, 0x14, value | 0x87);
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printk_debug("FAN_CTL: reg = 0x%04x, writing value = 0x%02x\r\n",
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base + 0x14, value | 0x87);
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}
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#endif
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static void it8716f_init(device_t dev)
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{
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struct superio_ite_it8716f_config *conf;
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struct resource *res0, *res1;
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if (!dev->enabled) {
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return;
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}
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conf = dev->chip_info;
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/* TODO: FDC, PP, KBCM, MIDI, GAME, IR. */
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switch (dev->path.u.pnp.device) {
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case IT8716F_SP1:
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res0 = find_resource(dev, PNP_IDX_IO0);
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init_uart8250(res0->base, &conf->com1);
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break;
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case IT8716F_SP2:
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res0 = find_resource(dev, PNP_IDX_IO0);
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init_uart8250(res0->base, &conf->com2);
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break;
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case IT8716F_EC:
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res0 = find_resource(dev, PNP_IDX_IO0);
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#define EC_INDEX_PORT 5
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init_ec(res0->base + EC_INDEX_PORT);
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break;
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case IT8716F_KBCK:
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res0 = find_resource(dev, PNP_IDX_IO0);
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res1 = find_resource(dev, PNP_IDX_IO1);
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init_pc_keyboard(res0->base, res1->base, &conf->keyboard);
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break;
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}
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}
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static void it8716f_pnp_set_resources(device_t dev)
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{
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pnp_enter_ext_func_mode(dev);
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pnp_set_resources(dev);
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pnp_exit_ext_func_mode(dev);
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}
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static void it8716f_pnp_enable_resources(device_t dev)
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{
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pnp_enter_ext_func_mode(dev);
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pnp_enable_resources(dev);
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pnp_exit_ext_func_mode(dev);
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}
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static void it8716f_pnp_enable(device_t dev)
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{
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pnp_enter_ext_func_mode(dev);
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pnp_set_logical_device(dev);
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pnp_set_enable(dev, dev->enabled);
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pnp_exit_ext_func_mode(dev);
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}
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static struct device_operations ops = {
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.read_resources = pnp_read_resources,
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.set_resources = it8716f_pnp_set_resources,
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.enable_resources = it8716f_pnp_enable_resources,
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.enable = it8716f_pnp_enable,
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.init = it8716f_init,
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};
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static struct pnp_info pnp_dev_info[] = {
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{&ops, IT8716F_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0},},
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{&ops, IT8716F_SP1, PNP_IO0 | PNP_IRQ0, {0x7f8, 0},},
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{&ops, IT8716F_SP2, PNP_IO0 | PNP_IRQ0, {0x7f8, 0},},
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{&ops, IT8716F_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0},},
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{&ops, IT8716F_EC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x7f8, 0},
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{0x7f8, 0x4},},
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{&ops, IT8716F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x7ff, 0},
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{0x7ff, 0x4},},
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{&ops, IT8716F_KBCM, PNP_IRQ0,},
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{&ops, IT8716F_GPIO, PNP_IO1 | PNP_IO2, {0, 0}, {0x7f8, 0}, {0x7f8, 0},},
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{&ops, IT8716F_MIDI, PNP_IO0 | PNP_IRQ0, {0x7fe, 0x4},},
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{&ops, IT8716F_GAME, PNP_IO0, {0x7ff, 0},},
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{&ops, IT8716F_IR,},
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};
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static void enable_dev(struct device *dev)
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{
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pnp_enable_devices(dev, &ops,
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sizeof(pnp_dev_info) / sizeof(pnp_dev_info[0]), pnp_dev_info);
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}
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struct chip_operations superio_ite_it8716f_ops = {
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CHIP_NAME("ITE IT8716F Super I/O")
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.enable_dev = enable_dev,
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};
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