mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
561f7fcf67
Configure PCI root port as per schematic. Change-Id: I10ef682e8c54e22f328db5105d4da39c72ac2bed Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/19390 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
266 lines
9 KiB
Text
266 lines
9 KiB
Text
chip soc/intel/skylake
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# Deep Sx states
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register "deep_s3_enable_ac" = "0"
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register "deep_s3_enable_dc" = "0"
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register "deep_s5_enable_ac" = "1"
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register "deep_s5_enable_dc" = "1"
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register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN"
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# GPE configuration
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# Note that GPE events called out in ASL code rely on this
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# route. i.e. If this route changes then the affected GPE
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# offset bits also need to be changed.
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register "gpe0_dw0" = "GPP_B"
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register "gpe0_dw1" = "GPP_D"
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register "gpe0_dw2" = "GPP_E"
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# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
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register "gen1_dec" = "0x00fc0801"
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register "gen2_dec" = "0x000c0201"
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# EC memory map range is 0x900-0x9ff
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register "gen3_dec" = "0x00fc0901"
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# FSP Configuration
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register "ProbelessTrace" = "0"
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register "EnableLan" = "1"
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register "EnableSata" = "1"
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register "SataSalpSupport" = "1"
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register "SataMode" = "1"
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register "SataPortsEnable[0]" = "1"
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register "EnableAzalia" = "1"
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register "DspEnable" = "1"
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register "IoBufferOwnership" = "3"
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register "EnableTraceHub" = "0"
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register "XdciEnable" = "0"
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register "SsicPortEnable" = "0"
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register "SmbusEnable" = "1"
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register "Cio2Enable" = "0"
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register "ScsEmmcEnabled" = "0"
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register "ScsEmmcHs400Enabled" = "0"
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register "ScsSdCardEnabled" = "2"
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register "IshEnable" = "0"
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register "PttSwitch" = "0"
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register "InternalGfx" = "1"
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register "SkipExtGfxScan" = "1"
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register "Device4Enable" = "1"
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register "HeciEnabled" = "0"
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register "FspSkipMpInit" = "1"
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register "SaGv" = "3"
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register "SerialIrqConfigSirqEnable" = "1"
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register "PmConfigSlpS3MinAssert" = "2" # 50ms
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register "PmConfigSlpS4MinAssert" = "1" # 1s
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register "PmConfigSlpSusMinAssert" = "1" # 500ms
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register "PmConfigSlpAMinAssert" = "3" # 2s
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register "PmTimerDisabled" = "1"
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register "SendVrMbxCmd" = "1" # IMVP8 workaround
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register "pirqa_routing" = "PCH_IRQ11"
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register "pirqb_routing" = "PCH_IRQ10"
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register "pirqc_routing" = "PCH_IRQ11"
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register "pirqd_routing" = "PCH_IRQ11"
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register "pirqe_routing" = "PCH_IRQ11"
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register "pirqf_routing" = "PCH_IRQ11"
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register "pirqg_routing" = "PCH_IRQ11"
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register "pirqh_routing" = "PCH_IRQ11"
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# VR Settings Configuration for 4 Domains
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#+----------------+-------+-------+-------+-------+
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#| Domain/Setting | SA | IA | GTUS | GTS |
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#+----------------+-------+-------+-------+-------+
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#| Psi1Threshold | 20A | 20A | 20A | 20A |
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#| Psi2Threshold | 4A | 5A | 5A | 5A |
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#| Psi3Threshold | 1A | 1A | 1A | 1A |
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#| Psi3Enable | 1 | 1 | 1 | 1 |
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#| Psi4Enable | 1 | 1 | 1 | 1 |
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#| ImonSlope | 0 | 0 | 0 | 0 |
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#| ImonOffset | 0 | 0 | 0 | 0 |
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#| IccMax | 7A | 34A | 35A | 35A |
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#| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
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#+----------------+-------+-------+-------+-------+
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register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
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.vr_config_enable = 1,
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.psi1threshold = VR_CFG_AMP(20),
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.psi2threshold = VR_CFG_AMP(4),
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.psi3threshold = VR_CFG_AMP(1),
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.psi3enable = 1,
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.psi4enable = 1,
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.imon_slope = 0x0,
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.imon_offset = 0x0,
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.icc_max = VR_CFG_AMP(7),
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.voltage_limit = 1520,
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}"
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register "domain_vr_config[VR_IA_CORE]" = "{
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.vr_config_enable = 1,
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.psi1threshold = VR_CFG_AMP(20),
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.psi2threshold = VR_CFG_AMP(5),
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.psi3threshold = VR_CFG_AMP(1),
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.psi3enable = 1,
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.psi4enable = 1,
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.imon_slope = 0x0,
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.imon_offset = 0x0,
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.icc_max = VR_CFG_AMP(34),
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.voltage_limit = 1520,
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}"
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register "domain_vr_config[VR_GT_UNSLICED]" = "{
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.vr_config_enable = 1,
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.psi1threshold = VR_CFG_AMP(20),
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.psi2threshold = VR_CFG_AMP(5),
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.psi3threshold = VR_CFG_AMP(1),
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.psi3enable = 1,
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.psi4enable = 1,
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.imon_slope = 0x0,
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.imon_offset = 0x0,
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.icc_max = VR_CFG_AMP(35),
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.voltage_limit = 1520,
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}"
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register "domain_vr_config[VR_GT_SLICED]" = "{
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.vr_config_enable = 1,
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.psi1threshold = VR_CFG_AMP(20),
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.psi2threshold = VR_CFG_AMP(5),
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.psi3threshold = VR_CFG_AMP(1),
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.psi3enable = 1,
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.psi4enable = 1,
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.imon_slope = 0x0,
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.imon_offset = 0x0,
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.icc_max = VR_CFG_AMP(35),
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.voltage_limit = 1520,
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}"
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# Enable Root port 3(x1) for LAN.
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register "PcieRpEnable[2]" = "1"
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# Enable CLKREQ#
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register "PcieRpClkReqSupport[2]" = "1"
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# RP 3 uses SRCCLKREQ0#
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register "PcieRpClkReqNumber[2]" = "0"
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# Enable Root port 4(x1) for WLAN.
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register "PcieRpEnable[3]" = "1"
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# Enable CLKREQ#
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register "PcieRpClkReqSupport[3]" = "1"
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# RP 4 uses SRCCLKREQ5#
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register "PcieRpClkReqNumber[3]" = "5"
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# Enable Root port 5(x4) for NVMe.
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register "PcieRpEnable[4]" = "1"
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# Enable CLKREQ#
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register "PcieRpClkReqSupport[4]" = "1"
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# RP 5 uses SRCCLKREQ1#
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register "PcieRpClkReqNumber[4]" = "1"
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# Enable Root port 9 for BtoB.
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register "PcieRpEnable[8]" = "1"
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# Enable CLKREQ#
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register "PcieRpClkReqSupport[8]" = "1"
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# RP 9 uses SRCCLKREQ2#
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register "PcieRpClkReqNumber[8]" = "2"
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register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C
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register "usb2_ports[1]" = "USB2_PORT_MID(OC3)" # Type-A Rear
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register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # Type-A Front
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register "usb2_ports[3]" = "USB2_PORT_MID(OC2)" # Type-A Front
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register "usb2_ports[4]" = "USB2_PORT_MID(OC1)" # Type-A Rear
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register "usb2_ports[5]" = "USB2_PORT_MID(OC1)" # Type-A Rear
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register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
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register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type-A 2.0 / Debug
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register "usb2_ports[8]" = "USB2_PORT_EMPTY" # H1 (disconnected)
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register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C
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register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Rear
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register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Front
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register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Front
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register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Rear
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register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Rear
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register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3" # HDMI CEC
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register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3" # TPM
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register "i2c_voltage[2]" = "I2C_VOLTAGE_3V3" # Debug
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register "i2c_voltage[5]" = "I2C_VOLTAGE_1V8" # Audio
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# Must leave UART0 enabled or SD/eMMC will not work as PCI
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register "SerialIoDevMode" = "{
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[PchSerialIoIndexI2C0] = PchSerialIoPci,
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[PchSerialIoIndexI2C1] = PchSerialIoPci,
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[PchSerialIoIndexI2C2] = PchSerialIoPci,
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[PchSerialIoIndexI2C3] = PchSerialIoDisabled,
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[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
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[PchSerialIoIndexI2C5] = PchSerialIoPci,
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[PchSerialIoIndexSpi0] = PchSerialIoPci,
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[PchSerialIoIndexSpi1] = PchSerialIoDisabled,
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[PchSerialIoIndexUart0] = PchSerialIoPci,
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[PchSerialIoIndexUart1] = PchSerialIoDisabled,
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[PchSerialIoIndexUart2] = PchSerialIoSkipInit,
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}"
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register "speed_shift_enable" = "1"
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register "tdp_pl2_override" = "7"
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register "tcc_offset" = "10" # TCC of 90C
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# Use default SD card detect GPIO configuration
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register "sdcard_cd_gpio_default" = "GPP_A7"
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device domain 0 on
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device pci 00.0 on end # Host Bridge
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device pci 02.0 on end # Integrated Graphics Device
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device pci 14.0 on end # USB xHCI
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device pci 14.1 off end # USB xDCI (OTG)
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device pci 14.2 on end # Thermal Subsystem
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device pci 15.0 on
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end # I2C #0
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device pci 15.1 on end # I2C #1
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device pci 15.2 on end # I2C #2
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device pci 15.3 off
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end # I2C #3
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device pci 16.0 on end # Management Engine Interface 1
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.3 off end # Management Engine KT Redirection
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device pci 16.4 off end # Management Engine Interface 3
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device pci 17.0 on end # SATA
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device pci 19.0 on end # UART #2
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device pci 19.1 on
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end # I2C #5
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device pci 19.2 off end # I2C #4
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device pci 1c.0 off end # PCI Express Port 1
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device pci 1c.1 off end # PCI Express Port 2
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device pci 1c.2 on end # PCI Express Port 3 for LAN
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device pci 1c.3 on
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chip drivers/intel/wifi
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register "wake" = "GPE0_PCI_EXP"
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device pci 00.0 on end
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end
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end # PCI Express Port 4 for WLAN
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device pci 1c.4 on end # PCI Express Port 5 for NVMe
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device pci 1c.5 off end # PCI Express Port 6
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device pci 1c.6 off end # PCI Express Port 7
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device pci 1c.7 off end # PCI Express Port 8
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device pci 1d.0 on end # PCI Express Port 9 for BtoB
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device pci 1d.1 off end # PCI Express Port 10
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device pci 1d.2 off end # PCI Express Port 11
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device pci 1d.3 off end # PCI Express Port 12
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device pci 1e.0 on end # UART #0
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device pci 1e.1 off end # UART #1
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device pci 1e.2 on end # GSPI #0
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device pci 1e.3 off end # GSPI #1
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device pci 1e.4 off end # eMMC
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device pci 1e.5 off end # SDIO
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device pci 1e.6 on end # SDCard
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device pci 1f.0 on
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chip ec/google/chromeec
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device pnp 0c09.0 on end
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end
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end # LPC Interface
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device pci 1f.1 on end # P2SB
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device pci 1f.2 on end # Power Management Controller
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device pci 1f.3 on end # Intel HDA
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device pci 1f.4 on end # SMBus
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device pci 1f.5 on end # PCH SPI
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device pci 1f.6 off end # GbE
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end
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end
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